From: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com>
Add reset manager registers in preparation for F2S bridge reset
support as well as the mask support to enable/disable the bridges.
Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc
These bridges are available only in Stratix10:
BIT3: f2sdram0
BIT4: f2sdram1
BIT5: f2sdram2
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com>
---
.../include/mach/reset_manager_soc64.h | 18 +++++++++++++++---
arch/arm/mach-socfpga/misc_soc64.c | 2 +-
include/linux/intel-smc.h | 15 +++++++++++----
3 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index 058fdd6e548..4b010be9ee8 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -10,9 +10,12 @@
void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void print_reset_info(void);
-void socfpga_bridges_reset(int enable);
+void socfpga_bridges_reset(int enable, unsigned int mask);
#define RSTMGR_SOC64_STATUS 0x00
+#define RSTMGR_SOC64_HDSKEN 0x10
+#define RSTMGR_SOC64_HDSKREQ 0x14
+#define RSTMGR_SOC64_HDSKACK 0x18
#define RSTMGR_SOC64_MPUMODRST 0x20
#define RSTMGR_SOC64_PER0MODRST 0x24
#define RSTMGR_SOC64_PER1MODRST 0x28
@@ -20,8 +23,17 @@ void socfpga_bridges_reset(int enable);
#define RSTMGR_MPUMODRST_CORE0 0
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
-#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
-#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
+
+#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0)
+#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1)
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2)
+#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3)
+#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4)
+#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5)
+#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6)
+
+#define RSTMGR_HDSKEN_FPGAHSEN BIT(2)
+#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2)
/* SDM, Watchdogs and MPU warm reset mask */
#define RSTMGR_STAT_SDMWARMRST 0x2
diff --git a/arch/arm/mach-socfpga/misc_soc64.c
b/arch/arm/mach-socfpga/misc_soc64.c
index e0b2b4237e1..104b24241e4 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -107,5 +107,5 @@ void do_bridge_reset(int enable, unsigned int mask)
return;
}
- socfpga_bridges_reset(enable);
+ socfpga_bridges_reset(enable, mask);
}
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h
index a54eff43add..6455335bae4 100644
--- a/include/linux/intel-smc.h
+++ b/include/linux/intel-smc.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017-2018, Intel Corporation
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef __INTEL_SMC_H
@@ -482,10 +483,16 @@
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
* Call register usage:
* a0 INTEL_SIP_SMC_HPS_SET_BRIDGES
* a1 Set bridges status:
- * 0 - Disable
- * 1 - Enable
- * a2-7 not used
- *
+ * Bit 0: 0 - Disable, 1 - Enable
+ * Bit 1: 1 - Has mask value in a2
+ * a2 Mask value
+ * Bit 0: soc2fpga
+ * Bit 1: lwhps2fpga
+ * Bit 2: fpga2soc
+ * Bit 3: f2sdram0 (For Stratix 10 only)
+ * Bit 4: f2sdram1 (For Stratix 10 only)
+ * Bit 5: f2sdram2 (For Stratix 10 only)
+ * a3-7 not used
* Return status
* a0 INTEL_SIP_SMC_STATUS_OK
*/
--
2.25.1
