Hi Jagan,
>
>
> > -Original Message-
> > From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> > Sent: Friday, August 11, 2017 4:44 PM
> > To: Suresh Gupta
> > Cc: u-boot@lists.denx.de; Jagan Teki ;
> > york...@freescale.com; Anupam Kumar
>
t; From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Suresh
> Gupta
> Sent: Monday, June 12, 2017 7:33 PM
> To: Jagan Teki
> Cc: u-boot@lists.denx.de; Jagan Teki ; Yao Yuan
>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
&g
017 12:43 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] SPI NAND support
>
> On Tue, Sep 12, 2017 at 10:56 AM, Suresh Gupta
> wrote:
> > Hi All,
> >
> > Do we have NAND support in SPI framework. Please provide me pointers so
&g
Hi All,
Do we have NAND support in SPI framework. Please provide me pointers so that I
analyze/understand that for my purpose.
Thanks
SuresH
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Hi Jagan,
Do we have NAND support in our SPI framework of u-boot. Please provide me some
pointers if any so that I incorporate our controller with that driver.
Thanks
SuresH
___
U-Boot mailing list
U-Boot@lists.denx.de
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-by: Suresh Gupta
---
Change in v4:
- change Timeout from 1000ms to 100ms
Changes in v3:
- replace printf to debug
- return whatever return from wait_for_bit, before it was -EBUSY
Changes in v2:
- Add wait_for_bit instead of while
- move the busy check code to fsl_qspi_claim_bus form
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, August 30, 2017 7:54 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; York Sun
> Subject: Re: [PATCH v3] spi: fsl_qspi: Add controller busy check before new
> spi
> op
-by: Suresh Gupta
---
Chnages in v3:
- replace printf to debug
- return whatever return from wait_for_bit, before it was -EBUSY
Changes in v2:
- Add wait_for_bit instead of while
- move the busy check code to fsl_qspi_claim_bus form qspi_xfer
drivers/spi/fsl_qspi.c | 28
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, August 29, 2017 11:08 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; York Sun
> Subject: Re: [PATCH v2] spi: fsl_qspi: Add controller busy check before new
> spi
> op
For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.
Signed-off-by: Suresh Gupta
---
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
-by: Suresh Gupta
---
Changes in v2:
- Add wait_for_bit instead of while
- move the busy check code to fsl_qspi_claim_bus form qspi_xfer
drivers/spi/fsl_qspi.c | 28 +++-
drivers/spi/fsl_qspi.h | 4
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, August 23, 2017 10:57 AM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Jagan Teki
> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before
> new
> -Original Message-
> From: York Sun
> Sent: Tuesday, August 22, 2017 9:56 PM
> To: Suresh Gupta ; u-boot@lists.denx.de
> Cc: ja...@openedev.com; Prabhakar Kushwaha
>
> Subject: Re: [PATCH] spi: fsl_qspi: Add controller busy check before new spi
> operation
>
Thanks Jagan for reviewing the code.
Please find comments in line
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Monday, August 21, 2017 7:53 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Jagan Teki
> Subject: Re: [U-Boot] [PA
Hi York,
Can I delegate this patch to you? Delegate to Jagan (SPI Maintainer) delays the
acceptance process.
Thanks
SuresH
> -Original Message-
> From: Suresh Gupta [mailto:suresh.gu...@nxp.com]
> Sent: Monday, August 21, 2017 3:56 PM
> To: u-boot@lists.denx.de
> Cc
-off-by: Suresh Gupta
---
drivers/spi/fsl_qspi.c | 26 ++
drivers/spi/fsl_qspi.h | 4
2 files changed, 30 insertions(+)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1dfa89a..69e9712 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi
> -Original Message-
> From: Suresh Gupta
> Sent: Monday, June 12, 2017 2:18 PM
> To: 'Jagan Teki'
> Cc: Jagan Teki ; york sun ;
> u-boot@lists.denx.de; Jagan Teki ; Yao Yuan
>
> Subject: RE: [U-Boot] [PATCH] sf: Fix s25fs512s er
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Monday, June 12, 2017 11:37 AM
> To: Suresh Gupta
> Cc: Jagan Teki ; york sun ;
> u-boot@lists.denx.de; Jagan Teki ; Yao Yuan
>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs51
> >
> > So best way is to disable hybrid mode and configure flash in Uniform
> > Sector Architecture
>
> OK, then send patches to Linux and U-Boot will review and take other
> suggestions too.
>
Thanks Jagan,
I will send U-boot patches (after testing) by early next week.
My next point :) to d
> -Original Message-
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Wednesday, June 07, 2017 12:33 PM
> To: Suresh Gupta
> Cc: york sun ; Jagan Teki ; u-
> b...@lists.denx.de; Jagan Teki ; Yao Yuan
>
> Subject: Re: [U-Boot] [PATCH] sf: Fix
LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO
Signed-off-by: Suresh Gupta
Signed-off-by: Anupam Kumar
---
drivers/spi/fsl_qspi.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/spi
uresH
> -Original Message-
> From: york sun
> Sent: Friday, March 31, 2017 5:50 AM
> To: Suresh Gupta
> Cc: Mingkai Hu ; Jagan Teki
> ; Jagan Teki ; u-
> b...@lists.denx.de
> Subject: Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase
>
> On 03/27/201
LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO
Signed-off-by: Suresh Gupta
---
Changes in v3:
- Change multi-line comment style
Changes in v2:
- Change commit message
- Add "if" condition in replac
> -Original Message-
> From: york sun
> Sent: Tuesday, May 23, 2017 9:50 PM
> To: Suresh Gupta ; u-boot@lists.denx.de
> Cc: ja...@openedev.com
> Subject: Re: [PATCH] LS1012A: change the size of flash
>
> On 04/25/2017 02:20 AM, Suresh Gupta wrote:
> > LS10
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Friday, May 12, 2017 11:51 PM
> To: Yogesh Narayan Gaur ; Suresh Gupta
>
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option
>
> On 05/11
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Friday, May 12, 2017 11:23 PM
> To: Suresh Gupta ; Jagan Teki
>
> Cc: u-boot@lists.denx.de; Jagan Teki ; Yao Yuan
>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove S
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, April 27, 2017 10:18 PM
> To: Suresh Gupta ; Jagan Teki
>
> Cc: u-boot@lists.denx.de; Jagan Teki ; Yao Yuan
>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remov
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, April 27, 2017 4:35 AM
> To: Suresh Gupta ; Jagan Teki
>
> Cc: u-boot@lists.denx.de; Jagan Teki ; Yao Yuan
>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remov
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, April 26, 2017 1:01 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Jagan Teki ; york sun
> ; Yao Yuan
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and
LS1012A has S25FS512S flash of 64M size
Signed-off-by: Suresh Gupta
---
include/configs/ls1012a_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 0db926f..861cbc3 100644
--- a/include/configs
As per data sheet, S25FS512S support Uniform sector option
or erase size of 256 kbytes and Page Programming buffer of
256 or 512 Bytes. So, flag SECT_4K have no significance
for this flash.
Signed-off-by: Suresh Gupta
---
drivers/mtd/spi/spi_flash_ids.c | 2 +-
1 file changed, 1 insertion(+), 1
ls1012ardb, ls1046ardb, ls2080ardb has S25FS512S
flash which do not support Bank Address Register commands
Signed-off-by: Suresh Gupta
---
include/configs/ls1012a_common.h | 1 -
include/configs/ls1046ardb.h | 1 -
include/configs/ls2080ardb.h | 1 -
3 files changed, 3 deletions
Hello Jagan,
[snip]
> >
> > Sorry for the late, It's better to not relay on specific flash and do
> > the 4-byte addressing. So, I've sent some patches based on this [1]
> > and will send the next version to wind-up all these changes. Please wait
> > some
> time.
> >
Any update on supporting 4
OK York, will send new patch..
> -Original Message-
> From: york sun
> Sent: Tuesday, February 28, 2017 9:56 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Scott Wood ; Leo Li
> ; Sriram Dash ; Rajesh Bhagat
>
> Subject: Re: [PATCH v3 4/8] armv8: Add work
> -Original Message-
> From: york sun
> Sent: Friday, February 24, 2017 10:31 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Scott Wood ; Leo Li
> ; Sriram Dash ; Rajesh Bhagat
>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
>
11:18 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Scott Wood ; Leo Li
> ; Sriram Dash ; Rajesh Bhagat
>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
>
> On 02/16/2017 01:12 PM, mailto:york@nxp.com wrote:
> > On 02/
SOC’s like LS1012A has only one chip select signal out to connect
with flash and the 64M flash is attached to it. On boards the same
CS is connected to different flash via mux.
So at one time only one flash is active and it is not possible to
scan other flash at run time.
Suresh Gupta (2
SOC’s like LS1012A has only one chip select signal
out to connect with flash. So at one time only one
flash is active and it is not possible to scan other
flash at run time.
Signed-off-by: Suresh Gupta
---
drivers/spi/fsl_qspi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
LS1012A has only one chip select signal out to
connect with flash
Signed-off-by: Suresh Gupta
---
arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index ed5ea54..23b3cec 100644
--- a
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2:
Clean up the
From: Suresh Gupta
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed
From: Suresh Gupta
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2
Sensitivity Compliance test
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++
arch/arm/cpu/armv8/fsl-layerscape/soc.c
-by: Suresh Gupta
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25 ++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6
The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY
Suresh Gupta (8):
armv8: Add workaround for USB erratum A-009008
armv8: Add workaround for USB erratum A-009798
armv8: Add workaround for USB erratum A
From: Suresh Gupta
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
: Suresh Gupta
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 29 ++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4
From: Suresh Gupta
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.
Signed-off-by: Sriram Dash
Signed-off-by
From: Suresh Gupta
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.
Signed-off-by: Sriram Dash
Signed-off-by
From: Suresh Gupta
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2
The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY
Suresh Gupta (8):
armv8: Add workaround for USB erratum A-009008
armv8: Add workaround for USB erratum A-009798
armv8: Add workaround for USB erratum A
From: Suresh Gupta
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2
From: Suresh Gupta
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High
From: Suresh Gupta
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
Signed-off-by: Suresh Gupta
---
Changes in v2
From: Suresh Gupta
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed
From: Suresh Gupta
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
From: Suresh Gupta
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High
From: Suresh Gupta
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.
Signed-off-by: Sriram Dash
Signed-off-by
The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY
Suresh Gupta (8):
armv8: Add workaround for USB erratum A-009008
armv8: Add workaround for USB erratum A-009798
armv8: Add workaround for USB erratum A
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/ar
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/ar
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.
Signed-off-by: Sriram Dash
---
arch/arm/cpu/armv7/ls102xa/Kconfig
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/ar
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++
arch
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/armv7/ls102xa/Kconfig| 4
arch
threshold to be above 525mV by using this workaround.
Signed-off-by: Suresh Gupta
---
Changes for v2:
- Incorporated missing SOC's affected by errata
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 62 +++
threshold to be above 525mV by using this workaround.
Signed-off-by: Suresh Gupta
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 62 +++
arch/powerpc/include/asm/config_mpc85xx.h | 7
arch/powerpc/include/asm
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