The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test
Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 29 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cceecf0..28a0015 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -23,6 +23,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -42,6 +43,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -71,6 +73,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -155,6 +158,9 @@ config SYS_FSL_ERRATUM_A010539
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1f460d7..8d86985 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -75,6 +75,25 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+ val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+ erratum_a009798();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -486,6 +506,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+ erratum_a009798();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 62d7046..8bd40e8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -342,6 +342,7 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR_USB2 0x07C
#define SCFG_USB3PRM1CR_USB3 0x088
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index c23c317..3537ecb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,7 @@
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
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