Fix a bug of 'commit 8104deb2d6b7 ("armv8: layerscape: Adjust memory
mapping for Flash/SD card on LS1046A")' as NAND block size is
256KB on LS1046AQDS.
Signed-off-by: Gong Qianyu
---
include/configs/ls1046a_common.h | 2 +-
include/configs/ls1046aqds.h | 2 +-
2 files c
Tested on ls1046ardb with automatically boot Ubuntu from SD card or
USB disk, if it fails to detect external storage disk, fall back to
qspi boot.
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
v2:
- No change.
configs/ls1046ardb_qspi_defconfig | 1 +
configs
Move the macro to defconfig to take effect globally.
Signed-off-by: Gong Qianyu
---
v2:
- Reordered the macro.
configs/ls1046aqds_SECURE_BOOT_defconfig| 1 +
configs/ls1046aqds_defconfig| 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
configs
Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.
Signed-off-by: Gong Qianyu
---
board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg | 2 +-
board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg | 2 +-
2 files changed, 2 insertions(+), 2 deletions
Tested on ls1046ardb with automatically boot Ubuntu from SD card or
USB disk, if it fails to detect external storage disk, fall back to
qspi boot.
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
configs/ls1046ardb_qspi_defconfig | 1 +
configs/ls1046ardb_sdcard_defconfig | 1
Move the macro to defconfig to take effect globally.
Signed-off-by: Gong Qianyu
---
configs/ls1046aqds_SECURE_BOOT_defconfig| 1 +
configs/ls1046aqds_defconfig| 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
configs/ls1046aqds_nand_defconfig
115200 bps for console
Signed-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v6:
- Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v5:
- Adjust the SPL BSS and MALLOC address.
v4:
- Extend SPL max size and pad_to size for SD boot.
v3
The SPL images are growing much bigger especially when DEBUG is ON.
So need to fix the values for them.
Signed-off-by: Gong Qianyu
---
include/configs/ls1043a_common.h | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/include/configs/ls1043a_common.h
115200 bps for console
Signed-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v6:
- Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v5:
- Adjust the SPL BSS and MALLOC address.
v4:
- Extend SPL max size and pad_to size for SD boot.
v3
10G ports
* Two SGMII ports
* Two RGMII ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong
From: Shengzhou Liu
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
v3-v6:
- No change.
v2:
- Add ERRATUM_A008511.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
1 file
From: Shaohui Xie
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3-v6:
- No change.
v2:
- Use values directly instead of macros.
- Revise commit message.
arch/arm/cpu
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly.
Clearing BSS and calling board_init_r() will be done in crt0_64.S.
Signed-off-by: Gong Qianyu
---
v6:
- No change.
v5:
- New Patch.
arch/arm
Signed-off-by: Gong Qianyu
---
v3-v6:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index
From: Shaohui Xie
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v6:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch
From: Shaohui Xie
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3-v6:
- No change.
v
e memory map in readme.
- Remove unused flash r/w functions.
- Remove DDR3 defines.
- Revise some commit messages.
Gong Qianyu (1):
armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r
Mingkai Hu (2):
armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
From: Shaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v6:
- No change.
drivers/ddr/fsl/fsl_ddr_gen4.c
From: Shaohui Xie
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3-v5:
- No change.
v
From: Shengzhou Liu
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
v3-v5:
- No change.
v2:
- Add ERRATUM_A008511.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
1 file
From: Shaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v5:
- No change.
drivers/ddr/fsl/fsl_ddr_gen4.c
10G ports
* Two SGMII ports
* Two RGMII ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong
115200 bps for console
Signed-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v5:
- Adjust the SPL BSS and MALLOC address.
v4:
- Extend SPL max size and pad_to size for SD boot.
v3:
- Remove redundant sd rcw .cfg files.
- Adjust the format of memory map.
- Add
From: Shaohui Xie
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3-v5:
- No change.
v2:
- Use values directly instead of macros.
- Revise commit message.
arch/arm/cpu
From: Shaohui Xie
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v5:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch
Signed-off-by: Gong Qianyu
---
v3-v5:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly.
Clearing BSS and calling board_init_r() will be done in crt0_64.S.
Signed-off-by: Gong Qianyu
---
v5:
- New Patch.
arch/arm/cpu/armv8/fsl-
in v2:
- Add ERRATUM_A008511.
- Use values directly instead of macros for SATA ECC.
- Add >60 characters' paragraph for the board help.
- Fix the memory map in readme.
- Remove unused flash r/w functions.
- Remove DDR3 defines.
- Revise some commit messages.
Gong Qianyu (1):
armv
From: Shaohui Xie
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3-v4:
- No change.
v2:
- Use values directly instead of macros.
- Revise commit message.
arch/arm/cpu
From: Shaohui Xie
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3-v4:
- No change.
v
115200 bps for console
Signed-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v4:
- Extend SPL max size and pad_to size for SD boot.
v3:
- Remove redundant sd rcw .cfg files.
- Adjust the format of memory map.
- Add emmc boot support.
v2:
- Add >60 charact
Signed-off-by: Gong Qianyu
---
v3-v4:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index
10G ports
* Two SGMII ports
* Two RGMII ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong
Hi all,
This is version 4 patchset mainly to add support for both LS1046ARDB&QDS board.
It should be based on two DDR patches to work well on LS1046ARDB or LS1046AQDS.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/
PCIe and USB are not sup
From: Shaohui Xie
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v4:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch
From: Shaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v4:
- No change.
drivers/ddr/fsl/fsl_ddr_gen4.c
From: Shengzhou Liu
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
v3-v4:
- No change.
v2:
- Add ERRATUM_A008511.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
1 file
The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu
Reviewed-by: Jagan Teki
Reviewed-by: Joe Hershberger
---
v2:
- Revised the comments as per
From: Shengzhou Liu
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
v3:
- No change.
v2:
- Add ERRATUM_A008511.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
1 file
115200 bps for console
Signed-off-by: Gong Qianyu
Signed-off-by: Mingkai Hu
---
v3:
- Remove redundant sd rcw .cfg files.
- Adjust the format of memory map.
- Add emmc boot support.
v2:
- Add >60 characters' paragraph for the board help.
- Fix the memory map in readme.
- Remov
From: Shaohui Xie
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3:
- No change.
v2:
- Use values directly instead of macros.
- Revise commit message.
arch/arm/cpu
Signed-off-by: Gong Qianyu
---
v3:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73
From: Shaohui Xie
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v3:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch
From: Shaohui Xie
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3:
- No change.
v
Hi all,
This is version 3 patchset mainly to add support for LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/
PCIe and USB are not supported yet due to lack
From: Shaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v3:
- No change.
drivers/ddr/fsl/fsl_ddr_gen4.c
From: Shaohui Xie
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2:
- Use values directly instead of macros.
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape
From: Shengzhou Liu
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
v2:
- Add ERRATUM_A008511.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
1 file changed, 6 insertions
Signed-off-by: Gong Qianyu
---
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
From: Shaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2:
- No change.
drivers/ddr/fsl/fsl_ddr_gen4.c | 7
115200 bps for console
Signed-off-by: Gong Qianyu
Signed-off-by: Mingkai Hu
---
v2:
- Add >60 characters' paragraph for the board help.
- Fix the memory map in readme.
- Remove unused flash r/w functions.
- Remove DDR3 defines.
arch/arm/Kconfig
From: Shaohui Xie
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2:
- Revise commmi
From: Shaohui Xie
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch
Hi all,
This is version 2 patchset mainly to add support for LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/
PCIe and USB are not supported yet due to lack
Hi all,
This patchset mainly adds support for LS1046ARDB board. Tested on
LS1046ARDB board.
PCIe and USB are not supported yet due to lack of some driver patches
and I'll add them once they're ready for upstream.
Please help to review. Thanks!
Mingkai Hu (3):
drivers/ddr/fsl: add DEBUG_38
From: Shaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 7 ++-
1 file
From: Mingkai Hu
Use 3 cycles.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape
115200 bps for console
Signed-off-by: Gong Qianyu
Signed-off-by: Mingkai Hu
---
arch/arm/Kconfig | 9 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-ls1046a-rdb.dts | 44
arch/arm/dts/fsl-ls1046a.dtsi
From: Mingkai Hu
DEBUG_38 is needed for rev2 DDR controller.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
drivers/ddr/fsl/ctrl_regs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 24fd366..4ae8b80 100644
From: Shengzhou Liu
Enable ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Shaohui Xie
commit 952793150 'board/ls2085rdb: Export functions for standalone
AQ FW load apps' mentioned memset was exported but it was not,
this patch exports the memset.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
include/_exports.h | 1 +
include/exports.h
From: Shaohui Xie
So to fix SATA CRC error.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index
From: Shaohui Xie
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape
The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu
Reviewed-by: Jagan Teki
---
v2:
- Revised the comments as per Jagan's advice.
drivers/n
QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is
enabled, IFC would not be initialized correctly. So disable the IFC
node for Linux.
Signed-off-by: Gong Qianyu
---
v3:
- Moved the fixup to board file.
- Detected the muxing through QIXIS at runtime.
- Tested on LS1043AQDS board
When using SPI driver model, it will get the values from DT. So
there is no need to set CONFIG_ENV_SPI_MAX_HZ and
CONFIG_ENV_SPI_MODE any more.
Signed-off-by: Gong Qianyu
---
include/configs/ls1012a_common.h | 2 --
include/configs/ls1043a_common.h | 2 --
2 files changed, 4 deletions(-)
diff
The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu
---
drivers/net/fm/fm.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers
receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
Reviewed-by: Masahiro
detection
Gong Qianyu (2):
armv8: fsl-layerscape: Consolidate the LSCH2 common defines
armv8: fsl_lsch2: Add SerDes 2 support
Mingkai Hu (2):
armv8: fsl_lsch2: Add LS1046A SoC support
drivers: net/fm: Add Fman support for LS1046A
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4
From: Mingkai Hu
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Mihai Bantea
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
v3:
- No change.
v2:
- Move
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu
---
v3:
- Revise commit message.
v2:
- New Patch.
arch/arm/cpu/armv8/fsl
From: Alison Wang
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
v3:
- Revise commit message.
v2:
- Added commit messages.
arch/arm/cpu/armv8
Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.
Signed-off-by: Gong Qianyu
---
v3:
- New Patch.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 59 ---
1 file changed
From: Mingkai Hu
The Fman module on LS1046A is similiar with that on LS1043A but
LS1046A has one more XFI (10GbE) interface.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
v3:
- Revise commit message.
v2:
- Add commit messages.
drivers/net/fm/Makefile
This patch adds serdes 2 support for FSL_LSCH2.
Signed-off-by: Gong Qianyu
---
v2:
- New patch.
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 19 +++
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
.../arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
From: Alison Wang
Add support to detect Cortex-A72 core for printing it out.
Signed-off-by: Alison Wang
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
v2:
- Added commit messages.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 ++-
arch/arm/include/asm/arch-fsl
From: Mingkai Hu
This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
drivers/net/phy/aquantia.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
From: Mingkai Hu
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Mihai Bantea
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
v2:
- Move serdes 2 support to
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Change history:
[Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection
v2:
- Add commit messages.
[Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support
v2:
-
From: Mingkai Hu
This patch adds Fman support for LS1046A SoC.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
v2:
- Add commit messages.
drivers/net/fm/Makefile | 1 +
drivers/net/fm/ls1046.c | 123
2
From: Mingkai Hu
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Mihai Bantea
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff --git a/arch/arm/cpu/armv8/fsl
From: Alison Wang
Signed-off-by: Alison Wang
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8062106..b810d01 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu
From: Mingkai Hu
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 493cdc6..344fbe2 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
[PATCH 1/3] armv8: fsl-layerscape: Add A72 core detection
[PATCH 2/3] armv8/fsl_lsch2: Add LS1046A SoC support
[PATCH 3/3] armv8/ls1046a: Add Fman support
Regards,
Qi
From: Mingkai Hu
Data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
From: Mingkai Hu
Set the flash to Uniform Sector Architecture in the non-volatile
register. After the power cycle, it's also Uniform Sector Architecture.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 64
From: Mingkai Hu
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index f90c2ae..ad12f6d 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -147,6 +147,32 @@ struct phy_driver aqr105_driver
Now I2C is initialized early enough to access FPGA so it supports to
show board info as early as other boot methods.
Signed-off-by: Gong Qianyu
---
include/configs/ls1043aqds.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
Get the clocks from FPGA through IFC or I2C. So it needs I2C early init
if booting with IFC disabled.
Signed-off-by: Gong Qianyu
---
board/freescale/ls1043aqds/ls1043aqds.c | 4
include/configs/ls1043aqds.h| 5 +++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git
The LBMAP switches on the board will tell which boot device is used.
Only QSPI boot is supported if the boot device is IFCCard.
Signed-off-by: Gong Qianyu
---
board/freescale/ls1043aqds/ls1043aqds.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/board/freescale
IFC is considered as a required component in Layerscape platforms' Linux.
But if IFC is not enabled in U-Boot on some boards, accessing IFC memory
space would cause kernel call trace. So disable IFC node in such cases.
Signed-off-by: Gong Qianyu
---
V2:
- Revised the title and message.
-
There is no MODE_FAT but MODE_FS. Fix it.
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv7/ls102xa/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
index 1dfbf54..0289058 100644
--- a/arch/arm/cpu
There is no MODE_FAT but MODE_FS. Fix it.
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 4c8a9a0..5883c00 100644
init_early_memctl_regs() will also be called in board_early_init_f().
So remove the duplicate call in spl code.
Signed-off-by: Gong Qianyu
---
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
b/arch/arm/cpu
gd->env_addr will be initialized in env_init() in
common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.
So no need to do it again.
Signed-off-by: Gong Qianyu
---
board/freescale/ls1043aqds/ls1043aqds.c | 4
board/freescale/ls1043ardb/ls1043ardb.c | 5 -
2 files changed, 9 deleti
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.
Signed-off-by: Gong Qianyu
---
board/freescale/ls1043ardb/ls1043ardb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b/board/freescale/ls1043ardb/ls1043ardb.c
index
The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.
Signed-off-by: Gong Qianyu
---
board/freescale/ls
IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS.
So this patch could fix 'sync abort' caused by autoboot that tries to
access IFC address.
Signed-off-by: Gong Qianyu
---
include/configs/ls1043a_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/
Signed-off-by: Gong Qianyu
---
include/configs/ls1043a_common.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 2432531..e900c50 100644
--- a/include/configs/ls1043a_common.h
+++ b/include
Signed-off-by: Gong Qianyu
---
include/configs/ls1043a_common.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index fd243b1..2432531 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs
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