On 10 April 2016 at 10:47, Marek Vasut wrote:
> On 04/09/2016 12:40 AM, George Broz wrote:
>> On 8 April 2016 at 05:36, Marek Vasut wrote:
>>> On 04/08/2016 07:16 AM, Stefan Roese wrote:
>>>> On 08.04.2016 01:51, George Broz wrote:
>>>>
>>&g
On 8 April 2016 at 05:36, Marek Vasut wrote:
> On 04/08/2016 07:16 AM, Stefan Roese wrote:
>> On 08.04.2016 01:51, George Broz wrote:
>>
>>
>>
>>>>>> Try with the attached patch (and probably with dcache off)
>>>>>
>>>>>
i << 2));
> + temp_dq_io_delay1 = readl(addr + (i << 2));
>
> if (shift_dq + temp_dq_io_delay1 > delay_max)
> - shift_dq = delay_max - temp_dq_io_delay2;
> + shift_dq = delay_max - temp_dq
RO(non_skip_value) \
> ((non_skip_value) & skip_delay_mask)
>
> -struct gbl_type *gbl;
> -struct param_type *param;
> +static struct gbl_type *gbl;
> +static struct param_type *param;
>
> static void set_failing_group_s
EL == 2, "%s:%d dm_calib: left=%d right=%d\n",
> + debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
>__func__, __LINE__, left_edge[0], right_edge[0]);
>
> /* Move DQS (back to orig). */
> @@ -3079,14 +3079,14 @@ rw_mgr_mem_calibrate_writes_center(const u32
> rank_bgn, const u32 write_group,
> scc_mgr_apply_group_dm_out1_delay(mid);
> writel(0, &sdr_scc_mgr->update);
>
> - debug_cond(DLEVEL == 2,
> + debug_cond(DLEVEL >= 2,
>"%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
>__func__, __LINE__, left_edge[0], right_edge[0],
>mid, dm_margin);
> /* Export values. */
> gbl->fom_out += dq_margin + dqs_margin;
>
> - debug_cond(DLEVEL == 2,
> + debug_cond(DLEVEL >= 2,
>"%s:%d write_center: dq_margin=%d dqs_margin=%d
> dm_margin=%d\n",
>__func__, __LINE__, dq_margin, dqs_margin, dm_margin);
>
> @@ -3745,27 +3745,27 @@ int sdram_calibration_full(void)
> printf("%s: Preparing to start memory calibration\n", __FILE__);
>
> debug("%s:%d\n", __func__, __LINE__);
> - debug_cond(DLEVEL == 1,
> + debug_cond(DLEVEL >= 1,
>"DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u
> vg/dqs=%u,%u ",
>rwcfg->mem_number_of_ranks,
> rwcfg->mem_number_of_cs_per_dimm,
>rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
>rwcfg->mem_virtual_groups_per_read_dqs,
>rwcfg->mem_virtual_groups_per_write_dqs);
> - debug_cond(DLEVEL == 1,
> + debug_cond(DLEVEL >= 1,
>"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
>rwcfg->mem_if_read_dqs_width,
> rwcfg->mem_if_write_dqs_width,
>rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
>iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
> - debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
> + debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
>iocfg->delay_per_dqs_en_dchain_tap,
> iocfg->dll_chain_length);
> - debug_cond(DLEVEL == 1,
> + debug_cond(DLEVEL >= 1,
>"max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
>iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
>iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
> - debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
> + debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
>iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
>iocfg->io_out2_delay_max);
> - debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
> + debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
>iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
>
> hc_initialize_rom_data();
> --
> 2.7.0
>
Tested on: SoCKit, DE0_Nano_SoC
Tested-by: George Broz
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scc_mgr_set_dm_out1_delay(i, 0);
> + }
>
> /* Multicast to all DM enables. */
> writel(0xff, &sdr_scc_mgr->dm_ena);
> --
> 2.7.0
>
Tested on: SoCKit, DE0_Nano_SoC
Tested-by: George Broz
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mask;
> } else {
> - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
> debug_cond(DLEVEL == 2,
>"write_test(%u,%u,ONE) : %u != %i => %i\n",
>write_group, use_dm, *bit_
read_group, delay, 1);
> - writel(0, &sdr_scc_mgr->update);
> }
>
> /**
> --
> 2.7.0
>
Tested on: SoCKit, DE0_Nano_SoC
Tested-by: George Broz
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_LINE__, i);
> - scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
> + scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
> }
> }
>
> --
> 2.7.0
>
Tested on: SoCKit, DE0_Nano_SoC
Tested-by: George Broz
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hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
>
> debug("sdram set rule start %x, %d\n", lo_addr_bits,
> prule->sdram_start);
> --
> 2.7.0
>
Tested on: SoCKit, DE0_Nano_SoC
Tested-by: George Broz
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mem_calibrate(void)
> writel(0x2, &phy_mgr_cfg->mux_sel);
>
> /* Start tracking manager. */
> - setbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
> + writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
>
> return pass;
&g
t;ctrl_cfg, 1 << 22);
> + setbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
>
> return pass;
> }
> --
> 2.7.0
>
Tested on: SoCKit, DE0_Nano_SoC
Tested-by: George Broz
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On 7 April 2016 at 16:36, Marek Vasut wrote:
> On 04/08/2016 01:31 AM, George Broz wrote:
>> On 7 April 2016 at 13:39, Marek Vasut wrote:
>>> On 04/07/2016 03:14 PM, George Broz wrote:
>>>> On 6 April 2016 at 19:05, Marek Vasut wrote:
>>>>&
On 7 April 2016 at 13:39, Marek Vasut wrote:
> On 04/07/2016 03:14 PM, George Broz wrote:
>> On 6 April 2016 at 19:05, Marek Vasut wrote:
>>> On 04/07/2016 03:42 AM, George Broz wrote:
>>>
>>> Hi,
>>>
>>>>>> U-Boot SPL 2016.03
On 6 April 2016 at 19:05, Marek Vasut wrote:
> On 04/07/2016 03:42 AM, George Broz wrote:
>
> Hi,
>
>>>> U-Boot SPL 2016.03 (Apr 05 2016 - 17:57:23)
>>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>>> drivers/ddr/altera/
On 6 April 2016 at 03:43, Marek Vasut wrote:
> On 04/06/2016 03:17 AM, George Broz wrote:
>> On 5 April 2016 at 17:45, Marek Vasut wrote:
>>> On 04/06/2016 02:31 AM, George Broz wrote:
>>>> On 5 April 2016 at 15:03, Marek Vasut wrote:
>>>>> On 04/05
On 5 April 2016 at 17:45, Marek Vasut wrote:
> On 04/06/2016 02:31 AM, George Broz wrote:
>> On 5 April 2016 at 15:03, Marek Vasut wrote:
>>> On 04/05/2016 10:33 AM, Phil Reid wrote:
>>>> On 27/03/2016 4:52 AM, Marek Vasut wrote:
>>>>&
On 5 April 2016 at 15:03, Marek Vasut wrote:
> On 04/05/2016 10:33 AM, Phil Reid wrote:
>> On 27/03/2016 4:52 AM, Marek Vasut wrote:
>>> On 03/22/2016 06:06 PM, Dinh Nguyen wrote:
On 03/20/2016 11:42 AM, Marek Vasut wrote:
>>
>> Sorry, I know that doesn't help. So let's walk
On 20 March 2016 at 09:49, Marek Vasut wrote:
> On 03/18/2016 10:22 PM, George Broz wrote:
>> On 18 March 2016 at 12:32, Marek Vasut wrote:
>>> On 03/18/2016 07:59 PM, George Broz wrote:
>>>> On 16 March 2016 at 18:35, Marek Vasut wrote:
>>>>&
On 20 March 2016 at 08:55, Dinh Nguyen wrote:
>
>
> On 03/16/2016 08:35 PM, Marek Vasut wrote:
>>>
>>> Does this work for anybody else?
>>> Is it in anyone's experience that these (cheaper) Terasic
>>> eval boards are generally out of spec?
>>>
>>> Is there a way to relax the calibration parameter
On 16 March 2016 at 18:35, Marek Vasut wrote:
> On 03/16/2016 05:17 PM, George Broz wrote:
>> On 15 March 2016 at 18:29, George Broz wrote:
>>
>>>
>>> Hello again -
>>>
>>> So under the assumption my SoCKit h/w was broken, I bought a new boar
On 18 March 2016 at 12:32, Marek Vasut wrote:
> On 03/18/2016 07:59 PM, George Broz wrote:
>> On 16 March 2016 at 18:35, Marek Vasut wrote:
>>> On 03/16/2016 05:17 PM, George Broz wrote:
>>>> On 15 March 2016 at 18:29, George Broz wrote:
>>>>
>>
On 15 March 2016 at 18:29, George Broz wrote:
>
> Hello again -
>
> So under the assumption my SoCKit h/w was broken, I bought a new board.
> They are back ordered on SoCKit boards, so I got a DE0-Nano-SoC instead.
>
> I build the v2016.03 (release) version of u-boot-with-sp
On 9 March 2016 at 08:06, George Broz wrote:
> On 9 March 2016 at 02:55, Marek Vasut wrote:
>> On 03/09/2016 02:42 AM, Phil Reid wrote:
>>> G'day George,
>>>
>>> On 3/03/2016 10:57 PM, George Broz wrote:
>>>> On 2 March 2016 at 23:11, Phil
On 9 March 2016 at 02:55, Marek Vasut wrote:
> On 03/09/2016 02:42 AM, Phil Reid wrote:
>> G'day George,
>>
>> On 3/03/2016 10:57 PM, George Broz wrote:
>>> On 2 March 2016 at 23:11, Phil Reid wrote:
>>>> On 3/03/2016 2:49 PM, George Broz wrote:
On 3 March 2016 at 15:07, Marek Vasut wrote:
>> On 3 March 2016 at 14:42, Marek Vasut wrote:
>>> On 03/03/2016 11:27 PM, George Broz wrote:
>>>> Hi Marek,
>>>
>>> Hi!
>>>
>>>> Yes - would love to be using the SPL from 2016.01 for
On 3 March 2016 at 06:51, Marek Vasut wrote:
> On 03/03/2016 03:48 PM, Dinh Nguyen wrote:
>>
>>
>> On 03/02/2016 05:24 PM, Marek Vasut wrote:
>>>
>>> Well, that's our usual USB/QSPI cache issue that's tormenting your soul.
>>> CCing Chin ;-)
>>>
>>> Does the issue by any chance magically disappear
On 2 March 2016 at 23:11, Phil Reid wrote:
> On 3/03/2016 2:49 PM, George Broz wrote:
>>
>> On 1 March 2016 at 19:49, Phil Reid wrote:
>>>
>>> On 2/03/2016 10:40 AM, George Broz wrote:
>>>
>>>> Sorry for the delayed response - go
On 2 March 2016 at 23:11, Phil Reid wrote:
> On 3/03/2016 2:49 PM, George Broz wrote:
>>
>> On 1 March 2016 at 19:49, Phil Reid wrote:
>>>
>>> On 2/03/2016 10:40 AM, George Broz wrote:
>>>
>>>> Sorry for the delayed response - go
On 2 March 2016 at 14:54, Dinh Nguyen wrote:
>> socfpga_common.h and re-built the project. I picked up
>> spl/u-boot-spl-dtb.sfp and
>> u-boot-dtb.img and transferred them to the SD card with:
>>
>> dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0
>> dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k se
On 1 March 2016 at 19:49, Phil Reid wrote:
> On 2/03/2016 10:40 AM, George Broz wrote:
>
>> Sorry for the delayed response - got called away, but am back to this
>> now. I patched
>> socfpga_common.h and re-built the project. I picked up
>> spl/u-boot-spl-dtb
On 17 February 2016 at 18:45, Phil Reid wrote:
> G'day George
>
>
> On 18/02/2016 5:54 AM, George Broz wrote:
>>
>> Hello,
>>
>> Sorry for the newbie question...
>>
>> I have an Altera/Terasic board (socfpga_sockit) that has issues
>> rec
?
(I'm hoping the USB issues resolve themselves when I'm able to get
the later version of U-Boot running...)
Thanks for any input...
--George Broz
Moog Industrial Group
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