[U-Boot] [PATCH] 85xx: clean up the io_sel for PCI express of P1022

clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu --- arch/ppc/cpu/mpc8xxx/pci_cfg.c| 13 ++--- arch/ppc/include/asm/immap_85xx.h |5 + 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/ppc/cpu/mpc8xxx

[U-Boot] [PATCH v3 1/2] fsl_sata: Add the workaround for errata SATA-A001

After power on, the SATA host controller of P1022 Rev1 is configured in legacy mode instead of the expected enterprise mode. Software needs to clear bit[28] of HControl register to change to enterprise mode after bringing the host offline. Signed-off-by: Dave Liu --- * address Wolfgang&#

[U-Boot] [PATCH v3 2/2] fsl_sata: Move the snoop bit to another place

For P1022 SATA host controller, the data snoop bit of DW3 in PRDT is moved to bit28. Signed-off-by: Dave Liu --- * address Wolfgang's comments drivers/block/fsl_sata.h |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/block/fsl_sata.h b/drivers/

[U-Boot] [PATCH v2 1/2] fsl_sata: Add the workaround for errata SATA-A001

After power on, the SATA host controller of P1022 Rev1 is configured in legacy mode instead of the expected enterprise mode. Software needs to clear bit[28] of HControl register to change to enterprise mode after bringing the host offline. Signed-off-by: Dave Liu --- * address the second

[U-Boot] [PATCH v1 2/2] fsl_sata: Move the snoop bit to another place

For P1022 SATA host controller, the data snoop bit of DW3 in PRDT is moved to bit28. Signed-off-by: Dave Liu --- * address Kumar's comments drivers/block/fsl_sata.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_s

[U-Boot] [PATCH v1 1/2] fsl_sata: Add the workaround for errata SATA-A001

After power on, the SATA host controller of P1022 Rev1 is configured in legacy mode instead of the expected enterprise mode. Software needs to clear bit[28] of HControl register to change to enterprise mode after bringing the host offline. Signed-off-by: Dave Liu --- * address Kumar's com

[U-Boot] [PATCH 3/3] fsl_sata: Move the snoop bit to another place

For P1022 SATA host controller, the data snoop bit of DW3 in PRDT is moved to bit28. Signed-off-by: Dave Liu --- drivers/block/fsl_sata.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h index 18e88fa..75165ab 100644

[U-Boot] [PATCH 2/3] fsl_sata: Add the workaround for errata SATA-A001

After power on, the SATA host controller of P1022 Rev1 is configured in legacy mode instead of the expected enterprise mode. software needs to clear bit[28] of HControl register to change to enterprise mode after bringing the host offline. Signed-off-by: Dave Liu --- drivers/block/fsl_sata.c

[U-Boot] [PATCH v1 1/3] fsl-diu: Using I/O accessor to CCSR space

driver. Signed-off-by: Dave Liu Signed-off-by: Jerry Huang --- * address Timur's comments board/freescale/common/fsl_diu_fb.c | 55 ++- 1 files changed, 28 insertions(+), 27 deletions(-) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/c

[U-Boot] [PATCH] fsl-diu: Using I/O accessor to CCSR space

driver. Signed-off-by: Dave Liu Signed-off-by: Jerry Huang --- board/freescale/common/fsl_diu_fb.c | 55 ++- 1 files changed, 28 insertions(+), 27 deletions(-) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 2fc878b

[U-Boot] [PATCH] mpc8610hpcd: set the guarded bit to DBAT of system memory

. Report-by: Timur Tabi Signed-off-by: Dave Liu --- include/configs/MPC8610HPCD.h |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1d2d659..629c971 100644 --- a/include/configs/MPC8610HPCD.h +++ b

[U-Boot] [PATCH v1 2/2] fsl-ddr: change the default burst mode for DDR3

For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default. Signed-off-by: Dave Liu --- should go to B2.0.3 release. cpu/mpc8xxx/ddr/options.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/cpu/mpc8xxx/ddr/options.c

[U-Boot] [PATCH v1 1/2] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu --- cpu

[U-Boot] [PATCH] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for these turnarounds. Cutting down the turnaround from BL/2+4 to BL/2+2 will improve the memory performance. Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr/ctrl_regs.c |6 +++--- 1 files

[U-Boot] [PATCH] Fix the local bus divider mapping

The real clock divider is 4 times of the bits LCRR[CLKDIV], according the latest RevF RM. Signed-off-by: Dave Liu --- cpu/mpc85xx/speed.c |7 ++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 7959082..89ecc87 100644 --- a

[U-Boot] [PATCH 2/2] fsl-ddr: add override for the Rtt_WR

It may be different settings of Rtt_nom and Rtt_WR for different boards, adding the override provide the capability. Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++--- include/asm-ppc/fsl_ddr_sdram.h |1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff

[U-Boot] [PATCH 1/2] fsl-ddr: add the override for write leveling

add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++-- cpu/mpc8xxx/ddr/options.c |1 + include/asm-ppc/fsl_ddr_sdram.h |5 + 3 files changed, 20

[U-Boot] [PATCH] fsl-ddr: Fix power-down and ODT timing settings

MING_CFG_5[RODT_ON] should be set to WL-2 4. TIMING_CFG_5[RODT_OFF] should be set to WL-1 5. TIMING_CFG_5[WODT_ON] should be set to WL-2 6. TIMING_CFG_5[WODT_OFF] should be set to WL-1 ps: WL=TIMING_CFG_2[WR_LAT] The original work was finished by Mazyar Razzaz and Travis Wheatley. Signed-off-by

[U-Boot] [PATCH v1] fsl-ddr: Fix the chip-select interleaving issue

commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 introduced one new bug to chip-select interleaving. Single DDR controller also can do the chip-select interleaving if there is dual-rank or qual-rank DIMMs. Signed-off-by: Dave Liu --- The v1 also address the cs_per_ctrl == 1 case cpu/mpc8xxx

[U-Boot] [PATCH] fsl-ddr: Fix the chip-select interleaving issue

commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 introduced one new bug to chip-select interleaving. Single DDR controller also can do the chip-select interleaving if there is dual-rank or qual-rank DIMMs. Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr/options.c |4 +--- 1 files changed, 1

[U-Boot] [PATCH] 85xx: Enable the DDR3 SPD support for P2020DS board

* The ELPIDA 2GB unbuffered DDR3 SDRAM DIMMs - EBJ21EE8BAFA-AE-E 600MT/s, 667MT/s and 800MT/s passed on P2020DS * Micron 1GB unbuffered DDR3 SDRAM DIMMs - MT9JSF12872AY-1G4D1 600MT/s, 667MT/s and 800MT/s passed on P2020DS Signed-off-by: Dave Liu Signed-off-by: Travis Wheatley --- board

[U-Boot] [PATCH] 85xx: Fix the wrong SYS_CLK_IN for 8569MDS

The SYS_CLK_IN of MPC8569MDS is 66.66MHz, The DDR_CLK_IN is same with SYS_CLK_IN in 8569 processor. so, change the SYS_CLK_IN from 66MHz to 66.66MHz. Signed-off-by: Dave Liu --- include/configs/MPC8569MDS.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include

[U-Boot] [PATCH] 85xx: Fix the wrong BCSR address of 8569MDS

The BCSR17[7] = 1 will unlock the write protect of FLASH. The WP# pin only controls the write protect of top/bottom sector, That is why we can save env, but we can't write the first sector before the patch. Signed-off-by: Dave Liu --- board/freescale/mpc8569mds/bcsr.c |2 +- 1 files ch

[U-Boot] [PATCH] fs: Fix the wrong type of var

From: Gao Guanhua The filelen should be signed type, not unsigned type. otherwise, The condition as below never take. if (filelen < 0) Signed-off-by: Gao Guanhua Signed-off-by: Dave Liu --- common/cmd_ext2.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --gi

[U-Boot] [PATCH 2/2] 85xx: add the nfsboot/ramboot to default environment

Give the MPC8569MDS board one default environment var. Signed-off-by: Dave Liu --- include/configs/MPC8569MDS.h | 72 -- 1 files changed, 41 insertions(+), 31 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index

[U-Boot] [PATCH 1/2] 85xx: Fix the clock adjust of mpc8569mds board

Currently the clk_adj is 6 (3/4 cycle), The settings will cause the DDR controller hang at the data init. Change the clk_adj from 6 to 4 (1/2 cycle), make the memory system stable. Signed-off-by: Dave Liu --- board/freescale/mpc8569mds/ddr.c |2 +- 1 files changed, 1 insertions(+), 1

[U-Boot] [PATCH] 85xx: Fix the clock adjust of mpc8569mds board

Currently the clk_adj is 6 (3/4 cycle), The settings will cause the DDR controller hang at the data init. Change the clk_adj from 6 to 4 (1/2 cycle), make the memory system stable. Signed-off-by: Dave Liu --- board/freescale/mpc8569mds/ddr.c |2 +- 1 files changed, 1 insertions(+), 1

[U-Boot] [PATCH 2/2] fsl-ddr: add the DDR3 SPD infrastructure

- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu Signed-off-by: Travis Wheatley --- common/ddr_spd.c| 53 + cpu/mpc85xx

[U-Boot] [PATCH 1/2] fsl-ddr: Fix two bugs in the ddr infrastructure

1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund Signed-off-by: Dave Liu --- The patch is resent to

[U-Boot] [PATCH] fsl-ddr: Fix some bugs in the ddr infrastructure

. Reported-by: Joakim Tjernlund Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr/ctrl_regs.c | 11 ++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 292980d..5c3e383 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c

[U-Boot] [PATCH] 83xx: Fix some bugs in spd sdram code

DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. Reported-by: Joakim Tjernlund Signed-off-by: Dave Liu --- cpu/mpc83xx/spd_sdram.c | 26 +++--- 1 files changed, 23 insertions(+), 3 deletions(-) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx

[U-Boot] [PATCH] fsl-ddr: Fix two bugs in the ddr infrastructure

1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr

[U-Boot] [PATCH] 83xx: Fix some bugs in spd sdram code

: Dave Liu --- cpu/mpc83xx/spd_sdram.c | 23 --- 1 files changed, 20 insertions(+), 3 deletions(-) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 42a4e67..ecbc70c 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -319,7 +319,21 @@ long

[U-Boot] [RFC] nand boot for 85xx

--- The patch is to be done, It is only giving the context why move the definition of fsl_law from .c to .h. Makefile | 13 +- board/freescale/mpc8572ds/config.mk |5 + board/freescale/mpc8572ds/nand_boot.c | 75 board/freescale/

[U-Boot] [PATCH 3/3] Move the LAW definition to fsl_law.h

some code need the LAWAR_EN, make them sharable. Signed-off-by: Dave Liu --- Jon, The 86xx also is using the fsl_law code, Could you ack and let Andy pick up to 85xx tree? Thanks, Dave drivers/misc/fsl_law.c| 15 --- include/asm-ppc/fsl_law.h | 16 2 files

[U-Boot] [PATCH 2/3] 85xx: Fix the wrong CSIZE mask bit

The CSIZE is L1CFG0[56-63] in the e500 and e500mc core, so we should mask 0xff, not 0x1ff. Signed-off-by: Dave Liu --- cpu/mpc85xx/start.S |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 80f9677..cfa53c0 100644 --- a

[U-Boot] [PATCH 1/3] 85xx: Fix the boot window issue

h_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu --- cpu/mpc85xx/start.S | 16 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 8fa0ff7..80f96

[U-Boot] [PATCH v1] lib_ppc: rework the flush_cache

- It is possible to miss flush/invalidate the last cache line, we fix it at here. - add the volatile and memory clobber. They are pointed by Scott Wood. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- lib_ppc/cache.c | 36 +--- 1 files changed, 17 inse

[U-Boot] [PATCH v3] nand: Fix cache and memory inconsistent issue

using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. The patch fix the cache issue. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- Stefan, I

[U-Boot] [PATCH] lib_ppc: rework the flush_cache

- It is possible to miss flush/invalidate the last cache line, we fix it at here. - add the volatile and memory clobber. the bugs is pointed by Scott Wood. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- lib_ppc/cache.c | 36 +--- 1 files chang

[U-Boot] [PATCH] 85xx: fix the wrong DDR settings for MPC8572DS

The default DDR freq is 400MHz or 800M data rate, the old settings is pure wrong for the default case. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- include/configs/MPC8572DS.h | 26 +- 1 files changed, 13 insertions(+), 13 deletions(-) diff --git a/include/c

[U-Boot] [PATCH v2] nand: Fix cache and memory inconsistent issue

family is using the dcache lock, so all of dcache access is cache-inhibited. so you can't see the issue. - 85xx family is using dcache, icache enable, partial cache lock. you will see the issue. The patch fix the cache issue. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --

[U-Boot] [PATCH 5/5] 85xx: enable the auto self refresh for wake up ARP

The wake up ARP feature need use the memory to process wake up packet, we enable auto self refresh to support it. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- board/freescale/mpc8536ds/ddr.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/board/fre

[U-Boot] [PATCH 4/5] fsl-ddr: use the 1T timing as default configuration

For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- board/freescale/mpc8540ads/ddr.c |3 +++ board/freescale/mpc8544ds

[U-Boot] [PATCH 3/5] fsl-ddr: make the self refresh idle threshold configurable

to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 12 include/asm-ppc/fsl_ddr_sdram.h |4 2 files changed, 12 insertions(+), 4 deletions(-) diff --git

[U-Boot] [PATCH 2/5] fsl-ddr: clean up the ddr code for DDR3 controller

- The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 24 +--- include/asm-ppc/fsl_ddr_sdram.h |3 +++ 2 files changed, 16 insertions(

[U-Boot] [PATCH 1/5] fsl-ddr: update the bit mask for DDR3 controller

According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 12 1 files changed, 8 insertions(+), 4 deletions(-)

[U-Boot] [PATCH] fsl-ddr: update the bit mask for DDR3 controller

According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 12 1 files changed, 8 insertions(+), 4 deletions(-)

[U-Boot] [PATCH] mpc83xx: Improve the performance of DDR memory

n dial down these values without a problem, thereby decreasing the latency of memory a little. Signed-off-by: Howard Gregory <[EMAIL PROTECTED]> Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- include/configs/MPC8315ERDB.h | 12 ++-- 1 files changed, 6 insertions(+), 6 deletion

[U-Boot] [PATCH] mpc83xx: enable eLBC NAND support for MPC8315ERDB board

Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- include/configs/MPC8315ERDB.h | 12 +++- 1 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 1225270..64bb62a 100644 --- a/include/configs/MPC8315ERDB.h

[U-Boot] [PATCH 2/2] 85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM case

we need TLB entry for DDR at !SPD case. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- board/freescale/mpc8536ds/mpc8536ds.c |6 ++ board/freescale/mpc8572ds/mpc8572ds.c |6 ++ 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc85

[U-Boot] [PATCH 1/2] 85xx: remove the unused ddr_enable_ecc in the board file

The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- board/atum8548/atum8548.c

[U-Boot] [PATCH 5/5] 86xx: remove the redundant r2 global data pointer save

The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add the another global data pointer save, but in fact the global data pointer will be initialized in the board_init_r, so remove it such as the 85xx/83xx family. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc86xx/start.S |

[U-Boot] [PATCH 4/5] 86xx: remove the unused code for 86xx family

I believe these code was copied from 74xx family, but for 86xx, it is unused. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc86xx/start.S | 14 -- 1 files changed, 0 insertions(+), 14 deletions(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 3

[U-Boot] [PATCH 3/5] 86xx: remove the second DDR LAW setting for mpc8641hpcn

The DDR1 LAW will precedence the DDR2 LAW, so remove the second DDR LAW. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- board/freescale/mpc8641hpcn/law.c |3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc86

[U-Boot] [PATCH 2/5] 86xx: remove the unused ddr_enable_ecc in the board file

The DDR controller of 86xx processors have the ECC data init feature, and the new DDR code is using the feature, we don't need the way with DMA to init memory again. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 11 --- boar

[U-Boot] [PATCH 1/5] 86xx: Move the clear_tlbs before MMU turn on

We must invalidate TLBs before MMU turn on, but currently the code is not, if there are some stale TLB entry valid in the TLBs, it will cause strange issue. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc86xx/start.S |5 - 1 files changed, 4 insertions(+), 1 deletions(-)

[U-Boot] [PATCH] 86xx: Move the clear_tlbs before MMU turn on

We must invalidate TLBs before MMU turn on, but currently the code is not, if there are some stale TLB entry valid in the TLBs, it will cause strange issue. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc86xx/start.S |5 - 1 files changed, 4 insertions(+), 1 deletions(-)

[U-Boot] [PATCH] 74xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache

. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <[EMAIL PROTECTED]> also, the r2 is used as global data pointer. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/74xx_7xx/start.S |8 1 files changed, 4 inse

[U-Boot] [PATCH] 86xx: remove the unused definition

Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- include/configs/MPC8610HPCD.h |9 - include/configs/MPC8641HPCN.h | 11 --- 2 files changed, 0 insertions(+), 20 deletions(-) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 678e1e1..d

[U-Boot] [PATCH] 85xx: Fix the incorrect register used for DDR erratum1

for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- cpu/mpc85xx/ddr-gen3.c |9 ++--- 1 files changed, 6 insertions

[U-Boot] [PATCH] 85xx: remove unused config definition

Signed-off-by: Dave Liu <[EMAIL PROTECTED]> --- include/configs/MPC8536DS.h |8 include/configs/MPC8572DS.h | 10 -- 2 files changed, 0 insertions(+), 18 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 38be10d..dbddb63 100644