1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
We are setting the mode register MR0[A12]='1'
3. TIMING_CFG_5[RODT_ON] should be set to WL-2
4. TIMING_CFG_5[RODT_OFF] should be set to WL-1
5. TIMING_CFG_5[WODT_ON] should be set to WL-2
6. TIMING_CFG_5[WODT_OFF] should be set to WL-1
ps: WL=TIMING_CFG_2[WR_LAT]
The original work was finished by Mazyar Razzaz and Travis Wheatley.
Signed-off-by: Dave Liu <dave...@freescale.com>
Signed-off-by: Travis Wheatley <travis.wheat...@freescale.com>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 17 ++++++++++-------
1 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 2505041..2736006 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -188,12 +188,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
* The DDR3 spec has not tXARD,
* we use the tXP instead of it.
* tXP=max(3nCK, 7.5ns) for DDR3.
- * we use the tXP=6
* spec has not the tAXPD, we use
* tAXPD=8, need design to confirm.
*/
- act_pd_exit_mclk = 6;
- pre_pd_exit_mclk = 6;
+ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ act_pd_exit_mclk = picos_to_mclk(tXP);
+ /* Mode register MR0[A12] is '1' - fast exit */
+ pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
#else /* CONFIG_FSL_DDR2 */
@@ -962,10 +963,12 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
unsigned int wodt_off = 0; /* Write to ODT off */
#if defined(CONFIG_FSL_DDR3)
- rodt_on = 3; /* 2 clocks */
- rodt_off = 4; /* 4 clocks */
- wodt_on = 2; /* 1 clocks */
- wodt_off = 4; /* 4 clocks */
+ int wl = compute_cas_write_latency();
+
+ rodt_on = wl - 2;
+ rodt_off = wl - 1;
+ wodt_on = wl - 2;
+ wodt_off = wl - 1;
#endif
ddr->timing_cfg_5 = (0
--
1.6.4
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