Not all RISC-V boards will have memory below 4 GiB.
>
> A weak implementation of dram_init_banksize() exists in common/board_f.c.
>
> See the discussion in
> https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77ae...@canonical.com/T/
>
> Signed-off-by: Heinrich Schucha
On Thu, Sep 14, 2023 at 12:49 PM Heinrich Schuchardt wrote:
>
> On 9/14/23 08:48, Wu, Fei wrote:
> > On 9/14/2023 2:05 PM, Heinrich Schuchardt wrote:
> >>
> >>
> >> Am 14. September 2023 07:30:55 MESZ schrieb Fei Wu :
> >>> In order to enable PCIe passthrough on qemu riscv, the physical memory
> >
On Tue, Jul 4, 2023 at 5:44 AM Heinrich Schuchardt
wrote:
>
> Describe which numeric values can be used for as scratch options for
> OpenSBI.
>
> Signed-off-by: Heinrich Schuchardt
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> common/spl/Kconfig
9031705.15575-1-pal...@rivosinc.com/
The "ISA string node structure" does mention that "ISA string" is
"Null-terminated ASCII Instruction Set Architecture (ISA) string for this
hart. The format of the ISA string is defined in the RISC-V unprivileged
specification."
(Refer, page6 of
https:/
though, I don't really care.
> >
> >>
> >> Regards,
> >> Anup
> >>
> >>
> >>
> >>>
> >>> > Regards,
> >>> > Anup
> >>> >
> >>> >>
> >>> >> parser s
> >>
> >> Compared to riscv,isa, this proposed scheme promotes vendor extensions,
> >> oft touted as the strength of RISC-V, to first-class citizens.
> >> At present, extensions are defined as meaning what the RISC-V ISA
> >> specifications say
and a new
> riscv,isa-base property to replace the aspect of riscv,isa that is
> not represented by the new property - the base ISA implemented by a hart.
>
> As a starting point, add properties for extensions currently used in
> Linux.
>
> Finally, mark riscv,i
s consistency
> > than RVI do in terms of versioning, or no care about backwards
> > compatibility.
> > A boolean property allows us to assign explicit meanings on a per vendor
> > extension basis, backed up by a description of their meanings.
> >
> > fin
> > ===
&g
ec.adoc
>
> Signed-off-by: Anup Patel
> Signed-off-by: Kautuk Consul
> ---
> arch/riscv/Kconfig | 45
> arch/riscv/include/asm/semihosting.h | 11 ++
> arch/riscv/include/asm/spl.h | 1 +
> arch/riscv/lib/Makefile
BOOT_PRINTS.
>
> Link:
> https://github.com/riscv-software-src/opensbi/blob/master/docs/firmware/fw_dynamic.md
> Signed-off-by: Nikita Shubin
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> common/spl/Kconfig | 8
> common/spl/spl_opensbi.c |
Hi Rick,
On Thu, Jan 27, 2022 at 11:41 AM Anup Patel wrote:
>
> We can use same U-Boot binary compiled using qemu-riscv64_smode_defconfig
> on QEMU virt machine and QEMU spike machine. To achieve this, we need HTIF
> console support for U-Boot QEMU RISC-V board hence this series.
We can now use same U-Boot images on both QEMU virt machine and QEMU
spike machine so let's update the QEMU RISC-V documentation.
Signed-off-by: Anup Patel
---
doc/board/emulation/qemu-riscv.rst | 48 --
1 file changed, 32 insertions(+), 16 deletions(-)
diff --
1 only if CFI flash DT node is
present.
Fixes: d248627f9d42 ("riscv: qemu: Enable MTD NOR flash support")
Signed-off-by: Anup Patel
Reviewed-by: Rick Chen
---
board/emulation/qemu-riscv/qemu-riscv.c | 12
1 file changed, 12 insertions(+)
diff --git a/board/emulation/qemu-
Enable support for HTIF console so that we can use QEMU RISC-V U-Boot
on RISC-V emulators and ISS having it.
Signed-off-by: Anup Patel
Reviewed-by: Philipp Tomsich
Reviewed-by: Rick Chen
---
board/emulation/qemu-riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/emulation
Quite a few RISC-V emulators and ISS (including Spike) have host
transfer interface (HTIF) based console. This patch adds HTIF
based console driver for RISC-V platforms which depends totally
on DT node for HTIF register base address.
Signed-off-by: Anup Patel
Reviewed-by: Philipp Tomsich
PATCH3
- Updated QEMU RISC-V documentation in PATCH4
Anup Patel (4):
serial: Add RISC-V HTIF console driver
riscv: qemu: Enable HTIF console support
riscv: qemu: Implement is_flash_available() for MTD NOR
doc: qemu-riscv: Update documentation for QEMU spike machine
board/emulation/qemu-riscv
On Tue, Jan 25, 2022 at 3:16 PM Bin Meng wrote:
>
> On Tue, Jan 25, 2022 at 2:02 PM Anup Patel wrote:
> >
> > On Tue, Jan 25, 2022 at 10:33 AM Bin Meng wrote:
> > >
> > > On Sat, Jan 15, 2022 at 12:20 AM Anup Patel
> > > wrote:
> > >
On Tue, Jan 25, 2022 at 2:46 PM Bin Meng wrote:
>
> On Tue, Jan 25, 2022 at 2:00 PM Anup Patel wrote:
> >
> > On Tue, Jan 25, 2022 at 10:22 AM Bin Meng wrote:
> > >
> > > On Sat, Jan 15, 2022 at 12:20 AM Anup Patel
> > > wrote:
> > > >
On Tue, Jan 25, 2022 at 10:40 AM Bin Meng wrote:
>
> On Tue, Jan 18, 2022 at 6:56 PM Anup Patel wrote:
> >
> > On Tue, Jan 18, 2022 at 3:41 PM Bin Meng wrote:
> > >
> > > On Sat, Jan 15, 2022 at 12:20 AM Anup Patel
> > > wrote:
> > >
On Tue, Jan 25, 2022 at 10:33 AM Bin Meng wrote:
>
> On Sat, Jan 15, 2022 at 12:20 AM Anup Patel wrote:
> >
> > Currently, if MTD NOR is enabled then U-Boot tries to issue flash
> > commands even when CFI flash DT node is not present. This causes
> > access fault on
On Tue, Jan 25, 2022 at 10:22 AM Bin Meng wrote:
>
> On Sat, Jan 15, 2022 at 12:20 AM Anup Patel wrote:
> >
> > Quite a few RISC-V emulators and ISS (including Spike) have host
> > transfer interface (HTIF) based console. This patch adds HTIF
> > based console dri
On Tue, Jan 18, 2022 at 3:41 PM Bin Meng wrote:
>
> On Sat, Jan 15, 2022 at 12:20 AM Anup Patel wrote:
> >
> > We can use same U-Boot binary compiled using qemu-riscv64_smode_defconfig
> > on QEMU virt machine and QEMU spike machine. To achieve this, we need HTIF
> &
1 only if CFI flash DT node is
present.
Fixes: d248627f9d42 ("riscv: qemu: Enable MTD NOR flash support")
Signed-off-by: Anup Patel
---
board/emulation/qemu-riscv/qemu-riscv.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/board/emulation/qemu-riscv/qemu-riscv.
Enable support for HTIF console so that we can use QEMU RISC-V U-Boot
on RISC-V emulators and ISS having it.
Signed-off-by: Anup Patel
Reviewed-by: Philipp Tomsich
---
board/emulation/qemu-riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/emulation/qemu-riscv/Kconfig
b
Quite a few RISC-V emulators and ISS (including Spike) have host
transfer interface (HTIF) based console. This patch adds HTIF
based console driver for RISC-V platforms which depends totally
on DT node for HTIF register base address.
Signed-off-by: Anup Patel
Reviewed-by: Philipp Tomsich
-system-riscv64 -M spike -m 256M -display none -serial stdio \
-bios opensbi/build/platform/generic/firmware/fw_jump.bin -kernel \
./u-boot/u-boot.bin
These patch can be found in qemu_riscv_htif_v1 branch at:
https://github.com/avpatel/u-boot.git
Anup Patel (3):
serial: Add RISC-V HTIF console driver
s(+)
>
> diff --git a/.mailmap b/.mailmap
> index 8e69f20c3a..9b41d56937 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -20,6 +20,8 @@ Allen Martin
> Andreas Bießmann
> Andreas Bießmann
> Aneesh V
> +Anup Patel
> +Atish Patra
> Boris Brezillon
> Boris Brezillon
> Dirk Behme
> --
> 2.33.1
>
Hi Michael,
Set bootargs to "root=/dev/vda2 rootwait console=ttyS0 earlycon=sbi" in
U-Boot before doing bootm
Regards,
Anup
On Wed, 2 Dec, 2020, 12:51 Michael Opdenacker, <
michael.opdenac...@bootlin.com> wrote:
> Greetings,
>
> To prepare an embedded Linux demo (on RiscV), I'm trying to boot L
then the board config can set the CONFIG_DMA_ADDR_T_64BIT.
Please see above suggestion.
Regards,
Anup
>
> Regards
> Padmarao
>
> On Sun, Nov 15, 2020 at 5:40 PM Anup Patel wrote:
>>
>> On Tue, Nov 10, 2020 at 4:16 PM Padmarao Begari
>> wrote:
>> >
>> >
On Tue, Nov 10, 2020 at 4:15 PM Padmarao Begari
wrote:
>
> This patch set adds Microchip PolarFire SoC Icicle Kit support
> to RISC-V U-Boot.
>
> The patches are based upon latest U-Boot tree
> (https://gitlab.denx.de/u-boot/u-boot.git) at commit id
> 1ae955e3a58f46918ef99b0b6c562967ba1bf39e
>
> A
> + [ OK ] Started Flush Journal to Persistent Storage.
> + [ OK ] Started Create Static Device Nodes in /dev.
> + [ OK ] Reached target Local File Systems (Pre).
> +Mounting /var/volatile...
> +Starting udev Kernel Device Manager...
> + [ OK ] Mounted /var/volatile.
> +Starting Load/Save Random Seed...
> + [ OK ] Reached target Local File Systems.
> +Starting Create Volatile Files and Directories...
> + [ OK ] Started udev Kernel Device Manager.
> + [ OK ] Started Create Volatile Files and Directories.
> +Starting Network Time Synchronization...
> +Starting Update UTMP about System Boot/Shutdown...
> + [ OK ] Started Update UTMP about System Boot/Shutdown.
> + [ OK ] Started Network Time Synchronization.
> + [ 11.618575] random: crng init done
> + [ 11.622007] random: 7 urandom warning(s) missed due to ratelimiting
> + [ OK ] Started Load/Save Random Seed.
> + [ OK ] Reached target System Initialization.
> + [ OK ] Started Daily Cleanup of Temporary Directories.
> + [ OK ] Reached target System Time Set.
> + [ OK ] Reached target System Time Synchronized.
> + [ OK ] Reached target Timers.
> + [ OK ] Listening on D-Bus System Message Bus Socket.
> + [ OK ] Listening on dropbear.socket.
> + [ OK ] Reached target Sockets.
> + [ OK ] Reached target Basic System.
> + [ OK ] Started D-Bus System Message Bus.
> +Starting IPv6 Packet Filtering Framework...
> +Starting IPv4 Packet Filtering Framework...
> +Starting Login Service...
> + [ OK ] Started IPv6 Packet Filtering Framework.
> + [ OK ] Started IPv4 Packet Filtering Framework.
> + [ OK ] Reached target Network (Pre).
> +Starting Network Service...
> + [ OK ] Started Login Service.
> + [ 12.602455] macb 20112000.ethernet eth0: PHY
> [20112000.ethernet-:09] driver [Vitesse VSC8662] (irq=POLL)
> + [ 12.612795] macb 20112000.ethernet eth0: configuring for phy/sgmii
> link mode
> + [ 12.622153] pps pps0: new PPS source ptp0
> + [ OK 12.626725] macb 20112000.ethernet: gem-ptp-timer ptp clock
> registered.
> + 0m] Started Network Service.
> +Starting Network Name Resolution...
> + [ OK ] Started Network Name Resolution.
> + [ OK ] Reached target Network.
> + [ OK ] Reached target Host and Network Name Lookups.
> + [ OK ] Started Collectd.
> + [ OK ] Started Collectd.
> +Starting Permit User Sessions...
> + [ OK ] Started Permit User Sessions.
> + [ OK ] Started Getty on tty1.
> + [ OK ] Started Serial Getty on ttyS0.
> + [ OK ] Reached target Login Prompts.
> + [ OK ] Reached target Multi-User System.
> +Starting Update UTMP about System Runlevel Changes...
> + [ OK ] Started Update UTMP about System Runlevel Changes.
> +
> + OpenEmbedded nodistro.0 icicle-kit-es ttyS0
> +
> + icicle-kit-es login: [ 15.795564] macb 20112000.ethernet eth0: Link is
> Up - 1Gbps/Full - flow control tx
> + [ 15.803306] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> +
> + icicle-kit-es login: root
> + root@icicle-kit-es:~#
> --
> 2.17.1
>
Thanks for including "custom boot flow" documentation.
This looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
_addr = ofnode_read_u32_default(phandle_args.node,
> + "reg", -1);
> +
> macb->regs = (void *)pdata->iobase;
>
> macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
> --
> 2.17.1
>
Looks good to me.
Reviewed-by: Anup Patel
This patch also needs to be tested on SiFive Unleashed because it has
same ethernet controller.
Regards,
Anup
gt;tx_ring_dma));
> + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
> + macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
> + macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
> + }
>
> if (macb_is_gem(macb)) {
> /* Initialize DMA properties */
> diff --git a/drivers/net/macb.h b/drivers/net/macb.h
> index 9b16383eba..72b84ae96e 100644
> --- a/drivers/net/macb.h
> +++ b/drivers/net/macb.h
> @@ -768,5 +768,11 @@
> #define GEM_RX_CSUM_CHECKED_MASK 2
> #define gem_writel_queue_TBQP(port, value, queue_num) \
> writel((value), (port)->regs + GEM_TBQP(queue_num))
> +#define gem_writel_queue_TBQPH(port, value, queue_num) \
> + writel((value), (port)->regs + GEM_TBQPH(queue_num))
> +#define gem_writel_queue_RBQP(port, value, queue_num) \
> + writel((value), (port)->regs + GEM_RBQP(queue_num))
> +#define gem_writel_queue_RBQPH(port, value, queue_num) \
> + writel((value), (port)->regs + GEM_RBQPH(queue_num))
>
> #endif /* __DRIVERS_MACB_H__ */
> --
> 2.17.1
>
Looks good to me.
Reviewed-by: Anup Patel
We need to test this patch on SiFive Unleashed as well because
it has same ethernet controller.
Regards,
Anup
On Thu, Oct 22, 2020 at 1:22 PM Padmarao Begari
wrote:
>
> This doc describes the procedure to build, flash and
> boot Linux using U-boot on Microchip MPFS Icicle Kit.
>
> Signed-off-by: Padmarao Begari
> ---
> doc/board/index.rst | 1 +
> doc/board/microchip/index.rst |
>
> -/*
> - * Physical Memory Map
> - */
> -#define PHYS_SDRAM_0 0x8000 /* SDRAM Bank #1 */
> -#define PHYS_SDRAM_0_SIZE 0x4000 /* 1 GB */
> -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
> +#define CONFIG_STANDALONE_LOAD_ADDR 0x8020
>
> -/* Init Stack Pointer */
> -#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + 0x20)
> +/* Environment options */
>
> -#define CONFIG_SYS_LOAD_ADDR 0x8000 /* SDRAM */
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 0) \
> + func(DHCP, dhcp, na)
>
> -/*
> - * memtest works on DRAM
> - */
> +#include
>
> -/* When we use RAM as ENV */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0x\0" \
> + "initrd_high=0x\0" \
> + "kernel_addr_r=0x8400\0" \
> + "fdt_addr_r=0x8800\0" \
> + "scriptaddr=0x8810\0" \
> + "pxefile_addr_r=0x8820\0" \
> + "ramdisk_addr_r=0x8830\0" \
> + BOOTENV
>
> #endif /* __CONFIG_H */
> --
> 2.17.1
>
Apart from above, it looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Thu, Oct 22, 2020 at 12:52 PM Padmarao Begari
wrote:
>
> Read phy address from device tree and use it to find the phy device
> if not found then search in the range of 0 to 31.
>
> Signed-off-by: Padmarao Begari
> ---
> drivers/net/macb.c | 15 +++
> 1 file changed, 15 insertions(
On Thu, Oct 22, 2020 at 12:52 PM Padmarao Begari
wrote:
>
> Enable 64-bit DMA support in the macb driver when CONFIG_DMA_ADDR_T_64BIT
> is enabled. 32-bit DMA is enabled by default.
>
> Signed-off-by: Padmarao Begari
> ---
> drivers/net/macb.c | 46 ++
hw;
> + pfsoc_periph_clks[i].sys_base = base;
> + pfsoc_periph_clks[i].prate = clk_rate;
> + name = pfsoc_periph_clks[i].periph.name;
> + ret = clk_register(hw, PFSOC_PERIPH_CLOCK, name, parent_name);
> + if (ret)
> + ERR_PTR(ret);
> + id = pfsoc_periph_clks[i].periph.id;
> + clk_dm(id, hw);
> + }
> +
> + return 0;
> +}
> +
> +const struct clk_ops pfsoc_periph_clk_ops = {
> + .enable = pfsoc_periph_clk_enable,
> + .disable = pfsoc_periph_clk_disable,
> + .get_rate = pfsoc_periph_clk_recalc_rate,
> +};
> +
> +U_BOOT_DRIVER(pfsoc_periph_clock) = {
> + .name = PFSOC_PERIPH_CLOCK,
> + .id = UCLASS_CLK,
> + .ops= &pfsoc_periph_clk_ops,
> +};
> diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h
> b/include/dt-bindings/clock/microchip,pfsoc-clock.h
> new file mode 100644
> index 00..527cff1a28
> --- /dev/null
> +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020 Microchip Technology Inc.
> + * Padmarao Begari
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
> +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_
> +
> +#define CLK_CPU0
> +#define CLK_AXI1
> +#define CLK_AHB2
> +
> +#define CLK_ENVM 3
> +#define CLK_MAC0 4
> +#define CLK_MAC1 5
> +#define CLK_MMC6
> +#define CLK_TIMER 7
> +#define CLK_MMUART08
> +#define CLK_MMUART19
> +#define CLK_MMUART210
> +#define CLK_MMUART311
> +#define CLK_MMUART412
> +#define CLK_SPI0 13
> +#define CLK_SPI1 14
> +#define CLK_I2C0 15
> +#define CLK_I2C1 16
> +#define CLK_CAN0 17
> +#define CLK_CAN1 18
> +#define CLK_USB19
> +#define CLK_RESERVED 20
> +#define CLK_RTC21
> +#define CLK_QSPI 22
> +#define CLK_GPIO0 23
> +#define CLK_GPIO1 24
> +#define CLK_GPIO2 25
> +#define CLK_DDRC 26
> +#define CLK_FIC0 27
> +#define CLK_FIC1 28
> +#define CLK_FIC2 29
> +#define CLK_FIC3 30
> +#define CLK_ATHENA 31
> +#define CLK_CFM32
> +
> +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */
> --
> 2.17.1
>
There are few minor checkpatch warnings on this patch so can
you please fix those.
Apart from this, it looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
l-name = "VDD";
> + channel_enabled;
> + };
> + ch2: channel@1 {
> + uohms-shunt-res = <1>;
> + rail-name = "VDDA25";
> + channel_enabled;
> + };
> + ch3: channel@2 {
> + uohms-shunt-res = <1>;
> + rail-name = "VDD25";
> + channel_enabled;
> + };
> + ch4: channel@3 {
> + uohms-shunt-res = <1>;
> + rail-name = "VDDA";
> + channel_enabled;
> + };
> + };
> + };
> + emac0: ethernet@2011 {
> + compatible = "cdns,macb";
> + reg = <0x0 0x2011 0x0 0x2000>;
> + interrupt-parent = <&plic>;
> + interrupts = <64 65 66 67>;
> + mac-address = [00 00 00 00 00 00];
> + phy-mode = "sgmii";
> + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
> + clock-names = "pclk", "hclk";
> + status = "disabled";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy0: ethernet-phy@8 {
> + reg = <8>;
> + ti,fifo-depth = <0x01>;
> + };
> + };
> + emac1: ethernet@20112000 {
> + compatible = "cdns,macb";
> + reg = <0x0 0x20112000 0x0 0x2000>;
> + interrupt-parent = <&plic>;
> + interrupts = <70 71 72 73>;
> + mac-address = [00 00 00 00 00 00];
> + phy-mode = "sgmii";
> + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
> + clock-names = "pclk", "hclk";
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy1: ethernet-phy@9 {
> + reg = <9>;
> + ti,fifo-depth = <0x01>;
> + };
> + };
> + gpio: gpio@0x20122000 {
> + compatible = "microsemi,ms-pf-mss-gpio";
> + interrupt-parent = <&plic>;
> + interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25
> 26
> + 27 28 29 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44>;
> + gpio-controller;
> + clocks = <&clkcfg CLK_GPIO2>;
> + reg = <0x00 0x20122000 0x0 0x1000>;
> + reg-names = "control";
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> + };
> +};
> --
> 2.17.1
>
Apart from above, looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
MA_ADDR_T_64BIT
> +typedef u64 dma_addr_t;
> +#else
> typedef u32 dma_addr_t;
> +#endif
>
> typedef unsigned long phys_addr_t;
> typedef unsigned long phys_size_t;
> --
> 2.17.1
>
Apart from above, looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Oct 16, 2020 at 7:55 PM wrote:
>
> From: Padmarao Begari
>
> This doc describes the procedure to build, flash and
> boot Linux using U-boot on Microchip MPFS Icicle Kit.
>
> Signed-off-by: Padmarao Begari
> ---
> doc/board/index.rst | 1 +
> doc/board/microchip/index.r
On Fri, Oct 16, 2020 at 7:54 PM wrote:
>
> From: Padmarao Begari
>
> Add indexes for reset and clock control signals within the system register
> module of the Microchip PolarFire SoC.
This patch should be squashed into your PATCH7.
>
> Signed-off-by: Padmarao Begari
> ---
> .../dt-bindings/c
On Fri, Oct 16, 2020 at 7:54 PM wrote:
>
> From: Padmarao Begari
>
> Add device tree for Microchip PolarFire SoC Icicle Kit.
>
> Signed-off-by: Padmarao Begari
> ---
> arch/riscv/dts/Makefile | 1 +
> arch/riscv/dts/microchip-icicle-kit-a000.dts | 419 +++
On Fri, Oct 16, 2020 at 7:54 PM wrote:
>
> From: Padmarao Begari
>
> This patch set adds Microchip PolarFire SoC Icicle Kit support
> to RISC-V U-Boot.
>
> The patches are based upon latest U-Boot tree
> (https://gitlab.denx.de/u-boot/u-boot.git) at commit id
> 9dc6aef8c963ae17e1263b89c692792fce0
On Thu, Sep 3, 2020 at 4:23 PM Sean Anderson wrote:
>
> On 9/3/20 1:01 AM, Anup Patel wrote:
> > On Thu, Sep 3, 2020 at 8:19 AM Bin Meng wrote:
> >>
> >> Hi Anup,
> >>
> >> On Thu, Sep 3, 2020 at 10:46 AM Anup Patel wrote:
> >&
On Thu, Sep 3, 2020 at 8:19 AM Bin Meng wrote:
>
> Hi Anup,
>
> On Thu, Sep 3, 2020 at 10:46 AM Anup Patel wrote:
> >
> > On Thu, Sep 3, 2020 at 7:32 AM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Tue, Aug 18, 2020 at 6:03 PM S
On Thu, Sep 3, 2020 at 7:32 AM Bin Meng wrote:
>
> Hi Anup,
>
> On Tue, Aug 18, 2020 at 6:03 PM Sean Anderson wrote:
> >
> > On 8/18/20 5:22 AM, Bin Meng wrote:
> > > +Anup Patel
> > >
> > > On Wed, Jul 29, 2020 at 5:57 PM Sean Anderson wrote:
On Sun, Aug 16, 2020 at 3:49 PM Heinrich Schuchardt wrote:
>
> On 8/15/20 5:55 PM, Anup Patel wrote:
> > On Sat, Aug 15, 2020 at 8:37 PM Heinrich Schuchardt
> > wrote:
> >>
> >> Am 15. August 2020 16:06:41 MESZ schrieb Anup Patel :
> >>> On S
On Sat, Aug 15, 2020 at 8:37 PM Heinrich Schuchardt wrote:
>
> Am 15. August 2020 16:06:41 MESZ schrieb Anup Patel :
> >On Sat, Aug 15, 2020 at 12:57 AM Heinrich Schuchardt
> > wrote:
> >>
> >> On 8/14/20 8:38 PM, Anup Patel wrote:
> >> > On F
On Sat, Aug 15, 2020 at 12:57 AM Heinrich Schuchardt wrote:
>
> On 8/14/20 8:38 PM, Anup Patel wrote:
> > On Fri, Aug 14, 2020 at 11:35 PM Heinrich Schuchardt
> > wrote:
> >>
> >> On 14.08.20 19:52, Anup Patel wrote:
> >>> On Fri, Aug 14, 20
On Fri, Aug 14, 2020 at 11:35 PM Heinrich Schuchardt wrote:
>
> On 14.08.20 19:52, Anup Patel wrote:
> > On Fri, Aug 14, 2020 at 11:15 PM Heinrich Schuchardt
> > wrote:
> >>
> >> On the Kendryte K210 OpenBSI cannot emulate the rdtime instruction. So we
>
On Fri, Aug 14, 2020 at 11:15 PM Heinrich Schuchardt wrote:
>
> On the Kendryte K210 OpenBSI cannot emulate the rdtime instruction. So we
> have to use the Sifive CLINT driver to provide riscv_get_time() in SMODE.
Can you elaborate why ?
The rdtime instruction should generate an illegal instruct
0:47
> > >To: Pragnesh Patel
> > >Cc: U-Boot Mailing List ; Atish Patra
> > >; Palmer Dabbelt ; Paul
> > >Walmsley ; Jagan Teki
> > >; Troy Benjegerdes
> > >; Anup Patel ; Sagar
> > >Kadam ; Rick Chen
> > >Subject: Re: [PAT
d kernel memory: 236K
> + [4.282989] This architecture does not have kernel memory
> protection.
> + [4.289390] Run /init as init process
> + Starting syslogd: OK
> + Starting klogd: OK
> + Starting mdev...
> + /etc/init.d/S10mdev: line 9: can't create /proc/sys/kernel/hotplug:
> nonexistent directory
> + [4.354461] mmc0: host does not support reading read-only switch,
> assuming write-enable
> + [4.361778] mmc0: new SDHC card on SPI
> + [4.381184] mmcblk0: mmc0: SC16G 14.8 GiB
> + [4.424975] mmcblk0: p1 p2 p3
> + modprobe: can't change directory to '/lib/modules': No such file or
> directory
> + Initializing random number generator... [5.041362] random: dd:
> uninitialized urandom read (512 bytes read)
> + done.
> + Starting network: [5.240580] macb 1009.ethernet eth0: PHY
> [1009.ethernet-:00] driver [Microsemi VSC8541 SyncE] (irq=POLL)
> + [5.250752] macb 1009.ethernet eth0: configuring for phy/gmii
> link mode
> + udhcpc: started, v1.29.3
> + udhcpc: sending discover
> + [7.301682] macb 1009.ethernet eth0: Link is Up - 100Mbps/Full
> - flow control tx
> + [7.308726] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> + udhcpc: sending discover
> + udhcpc: sending discover
> + udhcpc: no lease, failing
> + FAIL
> + Starting dropbear sshd: [ 14.309152] random: dropbear:
> uninitialized urandom read (32 bytes read)
> + OK
> +
> + Welcome to Buildroot
> + buildroot login: root
> + Password:
> + #
> --
> 2.17.1
>
Otherwise looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Mar 13, 2020 at 3:52 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
> >
> > On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> > >
> > > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > > wrote
On Fri, Mar 13, 2020 at 3:52 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
> >
> > On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> > >
> > > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > > wrote
On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
>
> On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> wrote:
> >
> > Enable all cache ways from u-boot proper.
>
> U-Boot
>
> >
> > Signed-off-by: Pragnesh Patel
> > ---
> > board/sifive/fu540/Makefile | 1 +
> > board/sifive/fu540/cache.c | 20 +
On Mon, Jan 27, 2020 at 1:19 PM Pragnesh Patel
wrote:
>
>
> >-Original Message-----
> >From: Anup Patel
> >Sent: 25 January 2020 14:12
> >To: Jagan Teki
> >Cc: Pragnesh Patel ; Atish Patra
> >; Palmer Dabbelt ; U-
> >Boot-Denx
> >Su
almsley ( Sifive)
> >; Troy Benjegerdes ( Sifive)
> >; Anup Patel ; Sagar
> >Kadam
> >Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
> >
> >On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
> >wrote:
> >>
> >>
On Fri, Jan 24, 2020 at 5:49 PM Pragnesh Patel
wrote:
>
> Add ddr4 controller and phy related files
>
> Signed-off-by: Pragnesh Patel
> ---
> board/sifive/fu540/Makefile|4 +
> board/sifive/fu540/ddr.c | 868
> board/sifive/fu540/regconfig-ctl.h | 270
On Fri, Jan 24, 2020 at 12:21 PM Jagan Teki wrote:
>
> On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
> wrote:
> >
> > With sifive_fu540_spl_defconfig:
> >
> > U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> > u-boot-spl.bin) and runs in L2 LIM in machine mode and then lo
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
> index 702d803ad8..909a1bf300 100644
> --- a/board/sifive/fu540/MAINTAINERS
> +++ b/board/sifive/fu540/MAINTAINERS
> @@ -1,9 +1,10 @@
> SiFive FU540 BOARD
> M: Paul Walmsley
> -M: Palmer Dabbelt
540.c
> index b81003aa6f..7fde881e72 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -13,6 +13,8 @@
> #include
> #include
>
> +#include "cache.h"
> +
> /*
> * This define is a value used for error/unknown serial.
> * If we
t; +
> +#define DEVICESRESET_DDR_CTRL_RST_N(x)(((x) & 0x1) << 0)
> +#define DEVICESRESET_DDR_AXI_RST_N(x) (((x) & 0x1) << 1)
> +#define DEVICESRESET_DDR_AHB_RST_N(x) (((x) & 0x1) << 2)
> +#define DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3)
> +#define DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
> +
> +#define CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
> +
> +#endif // _SIFIVE_UX00PRCI_H
> diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
> index 2756ed5a77..ef3ae9b650 100644
> --- a/include/configs/sifive-fu540.h
> +++ b/include/configs/sifive-fu540.h
> @@ -11,6 +11,22 @@
>
> #include
>
> +#ifdef CONFIG_SPL
> +
> +#define CONFIG_SPL_MAX_SIZE0x0010
> +#define CONFIG_SPL_BSS_START_ADDR 0x8500
> +#define CONFIG_SPL_BSS_MAX_SIZE0x0010
> +#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SPL_BSS_START_ADDR + \
> +CONFIG_SPL_BSS_MAX_SIZE)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
> +
> +#define CONFIG_SPL_LOAD_FIT_ADDRESS0x8400
> +
> +#define CONFIG_SPL_STACK (0x0800 + 0x001D - \
> +GENERATED_GBL_DATA_SIZE)
> +
> +#endif
> +
> #define CONFIG_SYS_SDRAM_BASE 0x8000
> #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE +
> SZ_2M)
>
> @@ -24,6 +40,7 @@
>
> /* Environment options */
>
> +#ifndef CONFIG_SPL_BUILD
> #define BOOT_TARGET_DEVICES(func) \
> func(MMC, mmc, 0) \
> func(DHCP, dhcp, na)
> @@ -43,5 +60,6 @@
> #define CONFIG_PREBOOT \
> "setenv fdt_addr ${fdtcontroladdr};" \
> "fdt addr ${fdtcontroladdr};"
> +#endif
>
> #endif /* __CONFIG_H */
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
On Wed, Jan 22, 2020 at 10:08 AM Anup Patel wrote:
>
> On Mon, Jan 20, 2020 at 8:04 PM Pragnesh Patel
> wrote:
> >
> > Hi Anup,
> >
> > >-----Original Message-
> > >From: Anup Patel
> > >Sent: 20 January 2020 10:26
> > >To
On Mon, Jan 20, 2020 at 8:04 PM Pragnesh Patel
wrote:
>
> Hi Anup,
>
> >-Original Message-
> >From: Anup Patel
> >Sent: 20 January 2020 10:26
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Palmer Dabbelt
> >; Atish Patra
> >Su
On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
wrote:
>
> This patch provides sifive_fu540_spl_defconfig which can support
> U-boot SPL to boot from L2 LIM (0x0800_) and then boot U-boot
> FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper
> images from MMC boot devices.
>
> Wit
On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
wrote:
>
> Add header files needed for U-boot SPL
>
> Signed-off-by: Pragnesh Patel
First of all, PATCH7 and PATCH8 does not make sense.
Instead of PATCH7 and PATCH8, we should have following
patch breakup:
1. A PATCH for adding ddrregs.c,required
i
> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> index bec0d19134..9b59f4ee14 100644
> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> @@ -4,3 +4,21 @@
> */
>
> #include "fu540-c000-u-boot.dtsi"
> +
> +/ {
> + hfclk {
> + u-boot,dm-spl;
> + };
> +
> + rtcclk {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&qspi2 {
> +
> + mmc@0 {
> + u-boot,dm-spl;
> + };
> +
> +};
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
crc16.o
> +obj-$(CONFIG_MMC_SPI) += crc7.o
> obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o
> obj-y += net_utils.o
> endif
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
>
> .bss : {
> __bss_start = .;
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Jan 17, 2020 at 6:17 PM Pragnesh Patel
wrote:
>
> Add fu540 SoC specific header files
>
> Signed-off-by: Pragnesh Patel
> ---
> arch/riscv/include/asm/arch-fu540/cache.h | 42 ++
> arch/riscv/include/asm/arch-fu540/gpio.h | 14
> arch/riscv/include/asm/arch-fu540/otp.h
@@ -12,6 +12,9 @@ config SYS_CPU
> config SYS_CONFIG_NAME
> default "sifive-fu540"
>
> +config SYS_SOC
> + default "fu540"
> +
> config SYS_TEXT_BASE
> default 0x8000 if !RISCV_SMODE
> default 0x8020 if RISCV_SMODE
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
iowrite32(((write_data >> bit) & 1),
> + ®s->pdin);
> + mdelay(1);
> +
> + iowrite32(0x01, ®s->pwe);
> + mdelay(1);
> + iowrite32(0x00, ®s->pwe);
> + mdelay(1);
> + }
> + }
> +
> + iowrite32(0x00, ®s->pas);
> + }
> +
> + // shut down
> + iowrite32(0x00, ®s->pwe);
> + iowrite32(0x00, ®s->pprog);
> + iowrite32(0x00, ®s->pce);
> + iowrite32(0x00, ®s->ptm);
> +
> + iowrite32(0x00, ®s->ptrim);
> + iowrite32(0x00, ®s->pdstb);
> +
> + return 0;
> +}
> +
> +static int hifive_otp_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
> +
> + plat->regs = dev_read_addr_ptr(dev);
> + return 0;
> +}
> +
> +static const struct misc_ops hifive_otp_ops = {
> + .read = hifive_otp_read,
> + .write = hifive_otp_write,
> +};
> +
> +static const struct udevice_id hifive_otp_ids[] = {
> + { .compatible = "sifive,fu540-otp" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(hifive_otp) = {
> + .name = "hifive_otp",
> + .id = UCLASS_MISC,
> + .of_match = hifive_otp_ids,
> + .ofdata_to_platdata = hifive_otp_ofdata_to_platdata,
> + .platdata_auto_alloc_size = sizeof(struct hifive_otp_platdata),
> + .ops = &hifive_otp_ops,
> +};
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
wrote:
>
> Add descriptions about U-Boot SPL feature and how to build and run.
>
> Signed-off-by: Pragnesh Patel
> ---
> doc/board/sifive/fu540.rst | 370 +
> 1 file changed, 370 insertions(+)
>
> diff --git a/doc
On Fri, Jan 17, 2020 at 6:16 PM Pragnesh Patel
wrote:
>
> This series add support for SPL to FU540. This series depends on
> https://patchwork.ozlabs.org/patch/1196703/
> (riscv: dts: Add hifive-unleashed-a00 dts from Linux)
>
> U-Boot SPL can boot from L2 LIM (0x0800_) and jump to
> OpenSBI(F
On Tue, Dec 31, 2019 at 7:29 PM Pragnesh Patel
wrote:
>
> This series add support for SPL to FU540. This series depends on
> https://patchwork.ozlabs.org/patch/1196703/
> (riscv: dts: Add hifive-unleashed-a00 dts from Linux)
>
> U-Boot SPL can boot from L2 LIM (0x0800_) and jump to
> OpenSBI(F
On Fri, Dec 6, 2019 at 2:50 PM Rick Chen wrote:
>
> Hi Lukas,
>
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Wednesday, December 04, 2019 5:40 AM
> > To: u-boot@lists.denx.de
> > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; L
On Fri, Dec 6, 2019 at 2:50 PM Rick Chen wrote:
>
> Hi Lukas,
>
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Wednesday, December 04, 2019 5:40 AM
> > To: u-boot@lists.denx.de
> > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas A
On Fri, Dec 6, 2019 at 2:50 PM Rick Chen wrote:
>
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Wednesday, December 04, 2019 5:40 AM
> > To: u-boot@lists.denx.de
> > Cc: Rick Jian-Zhi Chen(陳建志); Anup Patel; Bin Meng; Lukas Auer; Anup Patel
&
gt; pass dtb during opensbi builds.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v4:
> > - Drop abosolete text
> >
> > configs/sifive_fu540_defconfig | 3 ++-
> > doc/board/sifive/fu540.rst | 5 +
> > 2 files changed,
/riscv/dts/hifive-unleashed-a00.dts | 96 +
> > 3 files changed, 348 insertions(+)
> > create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644
> > arch/riscv/dts/hifive-unleashed-a00.dts
> >
>
> Reviewed-by: Bin Meng
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
___
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U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
1-08 at 15:27 +0800, Rick Chen wrote:
> > > > > Hi Atish
> > > > >
> > > > > > Hi Atish
> > > > > >
> > > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> > > > > > > > Hi Anup
On Fri, Nov 8, 2019 at 6:53 AM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Thu, Nov 7, 2019 at 5:11 PM Rick Chen wrote:
> > >
> > > Hi Anup & Lukas
> > >
> > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道：
> > > >
> > > &
On Thu, Nov 7, 2019 at 5:14 PM Auer, Lukas
wrote:
>
> On Thu, 2019-11-07 at 16:14 +0530, Anup Patel wrote:
> > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > wrote:
> > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > > > On Thu, Nov 7, 2019 at
On Thu, Nov 7, 2019 at 5:11 PM Rick Chen wrote:
>
> Hi Anup & Lukas
>
> Anup Patel 於 2019年11月7日 週四 下午6:44寫道：
> >
> > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > wrote:
> > >
> > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
>
On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
wrote:
>
> On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote:
> > > Hi Anup
> > >
> > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote:
> > >
On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote:
> > >
> > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote:
> > > >
> > > > Hi Anup
&g
On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote:
>
> On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote:
> >
> > Hi Anup
> >
> > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote:
> > > >
> > > > Hi Anup
> > > >
On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote:
>
> Hi Anup
>
> > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote:
> > >
> > > Hi Anup
> > >
> > > >
> > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote:
> > >
On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote:
> > >
> > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote:
> > > >
> > > > Hi Anup
> > &g
On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote:
>
> On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote:
> >
> > Hi Anup
> >
> > >
> > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote:
> > > >
> > > > Hi Anup
> > > &
On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote:
> > >
> > > Hi Anup
> > >
> > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel
> > > >
On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote:
>
> Hi Anup
>
> > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote:
> > > >
> > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
> > > > >
> > > > > Hi Bin,
> > >
On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote:
>
> On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
> >
> > Hi Bin,
> >
> > Thanks for the critics. Comments below.
> > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > > Hi Rick,
>
On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
>
> Hi Bin,
>
> Thanks for the critics. Comments below.
> On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > Hi Rick,
> >
> > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > >
> > > > Hi Rick,
> > > >
> >
On Wed, Sep 11, 2019 at 7:28 AM Bin Meng wrote:
>
> Hi Marcus,
>
> On Tue, Sep 10, 2019 at 11:53 PM Marcus Comstedt wrote:
> >
> >
> > Hi Bin,
> >
> > Bin Meng writes:
> >
> > > So 4.14 definitely was an out-of-tree kernel
> >
> > Everything before 5.2 was out-of-tree.
> >
> >
> > > No one can g
might be little different due to U-Boot specific changes
in DTS.
Thoughts ??
Regards,
Anup
> -Original Message-
> From: Atish Patra
> Sent: Sunday, September 8, 2019 5:40 PM
> To: david.abdurachma...@sifive.com; Alistair Francis
> ; Anup Patel
> Cc: u-boot@l
On Wed, Aug 14, 2019 at 4:01 PM Bin Meng wrote:
>
> This reverts commit 1b0c9914cc75d1570359181ebd493cd5746cb0ed.
>
> Commit 1b0c9914cc75 ("net: macb: Fixed reading MII_LPA register")
> causes 100Mbps does not work any more with SiFive FU540 GEM on the
> HiFive Unleashed board. Revert it.
>
> Sign
+ }
> return 0;
> }
>
> --
> 2.7.4
>
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Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
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