On 3/14/25 03:19, muhammad.hazim.izzat.za...@altera.com wrote:
From: Muhammad Hazim Izzat Zamri
This patchset enable the capability to automatically perform
FPGA configuration when booting Linux FIT image via bootm command.
The FPGA configuration bitstream shall be packed within the
FIT imag
On 2025/4/6 08:24, Jonas Karlman wrote:
BOARD_LATE_INIT is already selected by ROCKCHIP_RK3568 so there is no
need to select it under any board target config.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3568/Kconfig | 1 -
1 file ch
On Mon, 7 Apr 2025 at 09:44, Heinrich Schuchardt
wrote:
>
> Since commit 53d5a221632e ("emulation: Use bloblist to hold tables")
> `make qemu-riscv64_smode_defconfig acpi.config && make` fails with
>
> qfw_acpi.c:146:(.text.evt_write_acpi_tables+0xc):
> undefined reference to `bloblist_add
Because we've already returned early in the event 'handle' is NULL we
don't need these extra not NULL checks. Remove them
Signed-off-by: Bryan Brattlof
---
Hello everyone!
I noticed the extra NULL check and decided to clean it up. They could be
considered an extra precaution but the other calls
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 +-
1 fi
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 2 +-
1 fi
The set_dfu_alt_info() function calls the ALLOC_CACHE_ALIGN_BUFFER()
macro to declare a `buf' variable pointer into an array allocated on the
stack. It then calls the memset() function to clear the useable portion
of the array using the idiomatic expression `sizeof(buf)'.
While this would indeed w
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
Each controller has an nr_pins member that is set either through the
rockchip_pin_ctrl struct or from the core (or both).
This is an issue because on RK3568, RK3588 and RV1126, the struct is
const, this means it shouldn't be modi
On Mon, Apr 07, 2025 at 02:17:46PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On Mon, 7 Apr 2025 at 12:22, Tom Rini wrote:
> >
> > On Mon, Apr 07, 2025 at 09:24:16AM -0600, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Mon, 7 Apr 2025 at 08:31, Tom Rini wrote:
> > > >
> > > > On Mon, Apr 07, 2025
Hi
Il lun 7 apr 2025, 22:03 Fabio Estevam ha scritto:
> On Mon, Apr 7, 2025 at 4:58 PM Michael Nazzareno Trimarchi
> wrote:
>
> > Can you review it and pick if needed?
>
> This is not assigned to me in patchwork as it is not i.MX related.
>
> Someone else needs to handle it.
>
I was thinking t
On 2025/4/8 06:47, Jonas Karlman wrote:
Add support for the two USB2.0 PHYs use in the RK3528 SoC.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: New patch
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 20 +++
1 file changed, 20 inser
On 2025/4/8 06:47, Jonas Karlman wrote:
Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.
Add initial support for the RK3528 GMAC variant.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: New patch
---
drivers/net/dwc_eth_qo
On 2025/4/8 06:46, Jonas Karlman wrote:
The 480m clk is controlled using regs in the PHY address space and not
in the USB GRF address space on e.g. RK3528 and RK3506.
Add a clkout_ctl_phy usb2phy_reg to handle enable/disable of the 480m
clk on these SoCs.
Signed-off-by: Jonas Karlman
Review
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 2 +-
1 fi
On 07-04-2025 21:47, Michael Nazzareno Trimarchi wrote:
Hi MIke
On Mon, Apr 7, 2025 at 3:42 PM Mike Looijmans
mailto:mike.looijm...@topic.nl>> wrote:
ping?
Maybe I should have added to the description that the Linux kernel
allows MTD partitions to specify a size "0" in the device-tree to mean
"
Drop unneeded spi.h header include from spinand.h, nothing included by
spi.h is actually used in this header and .c should correctly included
spi.h if actually needed.
Replace spi.h with linux/bitops.h as this is what is actually required
for spinand.h
Signed-off-by: Christian Marangi
---
inclu
On 2025/4/8 06:46, Jonas Karlman wrote:
Add a device tree node for the SARADC controller used by RK3528.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250304201642.831218-4-jo...@kwiboo.se
Signed-off-by: Heiko Stuebner
[ upstream commit: 6e58302c84ce90aadbecd41efe1f69098a6f
On 2025/2/11 14:13, FUKAUMI Naoki wrote:
Boot the Radxa ROCK 3B from the USB OTG port using rkflashtool[1] or
rkusbboot[2] and dfu-util.
1a. Download the TPL and SPL using rkflashtool
$ rkflashtool l < mkimage-in-simple-bin.mkimage-rockchip-tpl
$ rkflashtool L < mkimage-in-simple-bin.mkimage-
On 2025/2/11 14:13, FUKAUMI Naoki wrote:
Boot the Radxa ROCK Pi S from the USB OTG port using rkflashtool[1] or
rkusbboot[2] and dfu-util.
1a. Download the TPL and SPL using rkflashtool
$ openssl rc4 -provider legacy -K 7c4e0304550509072d2c7b38170d1711 \
< mkimage-in-simple-bin.mkimag
On 07/04/25 13:50:21, Christopher Obbard wrote:
> Hi Jorge,
>
> Long time no speak.
hey, yeah, Embedded Recipes 2023 I think.
>
> On Mon, 7 Apr 2025 at 13:05, Jorge Ramirez-Ortiz
> wrote:
> >
> > Update build instructions.
> >
> > Signed-off-by: Jorge Ramirez-Ortiz
> > Reviewed-by: Neil Arms
This was originally taken from Linux, but at this point it's an inline
function upstream and no longer a macro. Given that we just want to extract
the serial number from the MMC CID, let's just inline that specifically.
This is also the style used in the MMC core code within U-Boot.
Signed-off-by:
On 2025/4/8 06:46, Jonas Karlman wrote:
From: Chukun Pan
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Signed-off-by: Chukun Pan
Link: https://lore.kernel.org/r
On 2025/4/8 06:46, Jonas Karlman wrote:
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
CH340B for debug console use.
Add pinctrl for UART0 M0 pins used for serial console.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250228064024.320-6-jo...@kwibo
On Mon, Apr 07, 2025 at 04:30:44PM +0200, Caleb Connolly wrote:
>
>
> On 4/7/25 15:28, Sumit Garg wrote:
> > From: Sumit Garg
> >
> > Currently the msm_sdhci doesn't yet support DLL configurations which are
> > required to enable bus speeds greater that 100MHz. So disable HS200 mode
> > support
On 2025/4/8 06:46, Jonas Karlman wrote:
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the user button using a gpio-keys node.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250304201642.831218-3-jo...@kwiboo.se
Signed-off-by:
On 2025/4/8 06:46, Jonas Karlman wrote:
The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB).
Enable support for the onboard eMMC on Radxa E20C.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250305214108.1327208-4-jo...@kwiboo.se
Signed-off-by: Heiko Stueb
On 2025/4/6 08:24, Jonas Karlman wrote:
Ensure ROCKCHIP_DEVICE_SETTINGS is defined before including
rk3588_common.h in board include/configs files.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
include/configs/evb_rk3588.h | 4 ++--
include/configs/
On 2025/4/6 08:24, Jonas Karlman wrote:
BOARD_LATE_INIT is already selected by ROCKCHIP_RK3588 so there is no
need to select it under any board target config.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/rk3588/Kconfig | 20
On 2025/4/8 06:46, Jonas Karlman wrote:
From: Yao Zi
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs,
On 2025/4/8 06:47, Jonas Karlman wrote:
The Radxa E20C is an ultra-compact network computer with a RK3528A SoC
that offers a wide range of networking capabilities.
Features tested on a Radxa E20C v1.104:
- SD-card boot
- eMMC boot
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thank
On 2025/4/8 06:46, Jonas Karlman wrote:
From: Lin Jinhan
Add support for rkrng variant, used by e.g. RK3528 and RK3576.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments for mainline.
Signed-off-by: Lin Jinhan
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
On 2025/4/8 06:46, Jonas Karlman wrote:
Add support for the OTP controller in RK3528. The OTPC is similar to the
OTPC in RK3568 and can use the same ops for reading OTP data.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: New patch
---
drivers/misc/rockchip
On 2025/4/8 06:46, Jonas Karlman wrote:
Enable clock stopping to gate clock during phase code change to ensure
glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
on RK3528.
POST_CHANGE_DLY
Time taken for phase switching and stable clock output.
- Less than 4-cycle latency
PR
On 2025/4/8 06:46, Jonas Karlman wrote:
Add initial support for SDHCI controller in RK3528.
Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
more work is needed to get the faster HS200/HS400/HS400ES modes working.
Variant tap and delay num is copied from vendor Linux t
On 2025/4/8 06:46, Jonas Karlman wrote:
RK3528 and RK3576 use different tap and delay num for cmdout and strbin.
Move tap and delay num for cmdout and strbin to driver data to prepare
for adding new SoCs.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: No cha
On 2025/4/8 06:46, Jonas Karlman wrote:
Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.
Add initial arch support for the RK3528 SoC.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v2:
- Add FIREWALL_DDR handling to fix emmc/fspi/sdmmc/us
On 2025/4/8 06:46, Jonas Karlman wrote:
Add a rk3528-u-boot.dtsi extending the basic dts/upstream rk3528.dtsi
with bare minimum nodes to have a booting system from eMMC and SD-card.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changes in v2:
- Use more nodes fr
On 2025/4/8 06:46, Jonas Karlman wrote:
Radxa E20C has three gpio controlled leds (sys, wan and lan).
Add led nodes and set default trigger to heartbeat for the sys led and
netdev for the lan and wan leds.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250304201642.831218-2-j
On 2025/4/8 06:46, Jonas Karlman wrote:
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
Signed-off-by: Jonas Karlman
Link: https://lore
On 2025/4/8 06:46, Jonas Karlman wrote:
From: Yao Zi
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Signed-off-by: Yao Zi
Link: https://lore.kernel.org/r/20250217061142.3848
On 2025/4/8 06:46, Jonas Karlman wrote:
From: Yao Zi
Add missing clocks in UART nodes for RK3528 SoC.
Signed-off-by: Yao Zi
Link: https://lore.kernel.org/r/20250217061142.38480-10-zi...@disroot.org
Signed-off-by: Heiko Stuebner
[ upstream commit: b9454434d0349223418f74fbfa7b902104da9bc5 ]
On 2025/4/6 08:24, Jonas Karlman wrote:
The meminfo and rng commands are helpful for testing, enable them.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/generic-rk3588_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/generic-rk
On 2025/4/6 08:24, Jonas Karlman wrote:
The meminfo and rng commands are helpful for testing, enable them.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/generic-rk3568_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/generic-rk
On 2025/4/6 08:24, Jonas Karlman wrote:
Ensure ROCKCHIP_DEVICE_SETTINGS is defined before including
rk3568_common.h in board include/configs files.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
include/configs/anbernic-rgxx3-rk3566.h | 4 ++--
include/configs
On 2025/4/6 08:24, Jonas Karlman wrote:
The partitions env variable is using an outdated partition layout that
is typically expected to be used with older vendor miniloader blobs.
Rockchip devices will run fine using any partition layout if the first
16 MiB of MMC storage is ignored/skipped.
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rv1108.c | 2 +-
1 fi
Hey all,
It's release day and here's v2025.04. We had some last minute issues
reported, but then also resolved. I want to thank everyone that's
contributed to this release, not just in terms of code, but
documentation, testing and otherwise ensuring things go as smoothly as
they can.
In terms of
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 2 +-
1 fi
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-px30.c | 2 +-
1 file
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
There's no need to modify private data from the controller, so let's
make that struct const.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 +-
1 fi
On 2025/1/29 20:42, Quentin Schulz wrote:
From: Quentin Schulz
Each bank has a base_pin member that is only set in the core and never
used, so it can be removed.
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
On Mon, Apr 7, 2025 at 4:58 PM Michael Nazzareno Trimarchi
wrote:
> Can you review it and pick if needed?
This is not assigned to me in patchwork as it is not i.MX related.
Someone else needs to handle it.
Add U-Boot override for RB1 to for USB in host mode as OTG mode isn't
supported. Also, disable sdhc_2 as it's currently not supported, sdhc_1
works fine though.
Signed-off-by: Sumit Garg
---
arch/arm/dts/qrb2210-rb1-u-boot.dtsi | 11 +++
1 file changed, 11 insertions(+)
create mode 1006
On 2025/2/11 14:13, FUKAUMI Naoki wrote:
Boot the Radxa ROCK Pi E v1/v3 from the USB OTG port using
rkflashtool[1] or rkusbboot[2] and dfu-util.
1a. Download the TPL and SPL using rkflashtool
$ openssl rc4 -provider legacy -K 7c4e0304550509072d2c7b38170d1711 \
< mkimage-in-simple-bin.
On 2025/2/21 00:56, Quentin Schulz wrote:
From: Quentin Schulz
This was only used on RK3288 Chromebooks and the EVB.
If it follows the same pattern as for RK3399 Chromebooks where their
maintainer (Simon) agreed[1] to removal of u-boot.rom on the basis that
the generic u-boot-rockchip-spi.bi
On 2025/2/21 00:56, Quentin Schulz wrote:
From: Quentin Schulz
Essentially the only differences between u-boot-rockchip.bin and
u-boot-rockchip-spi.bin are the formatting of idbloader.img which is
handled by mkimage (via -T rkspi/rksd) and the offset at which U-Boot
proper is flashed, the con
On 2025/2/21 05:57, Jonas Karlman wrote:
The Rockchip RK3576 SoC uses a different DRAM base address, 0x4000,
compared to prior SoCs.
Add default options that should work when 0x4000 is used as DRAM
base address. Use same offsets as before, just below 64 MiB.
Signed-off-by: Jonas Karlm
On 2025/2/21 05:56, Jonas Karlman wrote:
A few Rockchip ARMv7 SoCs use 0x6000 as DRAM base address instead of
the more common 0x0 DRAM base address used on AArch64 SoCs.
Add default options that should work for these ARMv7 SoCs. Same offsets
as before are used, just below 64 MiB. Hex value
On 2025/2/21 05:56, Jonas Karlman wrote:
The ROCKCHIP_COMMON_STACK_ADDR Kconfig option was originally enabled
in the SoC specific Kconfig files to ease during the initial migration
to use common stack addresses.
All boards for the affected SoCs have been migrated to use common stack
addresses.
On 2025/2/21 05:56, Jonas Karlman wrote:
The stack-pointer addresses used with ROCKCHIP_COMMON_STACK_ADDR expect
that DRAM is initialized by TPL or ROCKCHIP_EXTERNAL_TPL, that SPL has
access to full DRAM and SPL is loaded to/executed from start of DRAM.
Add depends on to ensure use of the ROCK
On 2025/2/21 05:56, Jonas Karlman wrote:
The Kconfig symbol ROCKCHIP_COMMON_STACK_ADDR currently imply the
TPL_ROCKCHIP_COMMON_BOARD option when TPL=y. This is inconvenient for a
SoC with very limited SRAM to use a custom tpl.c together with the
common stack addresses.
Move any imply TPL_ROCKC
From: Fabio Estevam
Currently, Ethernet fails to probe due to the lack of a valid MAC address:
```
Net:
Error: ethernet@f8008000 No valid MAC address found.
No ethernet found.
```
Select CONFIG_NET_RANDOM_ETHADDR so that a random MAC address is generated
and Ethernet can work by default.
Sig
The eMMC on RB1 boards supports HS200 mode but currently the msm_shdci
driver in U-Boot is missing DLL configuration required for HS200 mode to
work. Hence disable HS200 for now until proper support is in place.
Apart from that, add DT override for USB to work in host mode as otg
mode isn't suppor
On Mon, Apr 07, 2025 at 09:18:12AM -0600, Simon Glass wrote:
> Hi Tom,
>
> On Mon, 7 Apr 2025 at 07:53, Tom Rini wrote:
> >
> > On Mon, Apr 07, 2025 at 01:07:34PM +1200, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Mon, 7 Apr 2025 at 10:48, Tom Rini wrote:
> > > >
> > > > On Mon, Apr 07, 2025
On Mon, Apr 7, 2025 at 3:39 AM Eugen Hristev wrote:
> I am not convinced.
> The purpose of this early UART would be to get output *before* the DM
> code would enable clocks, pins, etc, for exactly that purpose, early
> debug output.
> So to remove all this and make the initialization rely on the
The SDHCI controller in Rockchip RK3528 is similar to the one included
in RK3588.
Add device tree node for the SDHCI controller in RK3528.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250305214108.1327208-3-jo...@kwiboo.se
Signed-off-by: Heiko Stuebner
[ upstream commit: a98c
Hi MIke
On Mon, Apr 7, 2025 at 3:42 PM Mike Looijmans
wrote:
> ping?
>
> Maybe I should have added to the description that the Linux kernel
> allows MTD partitions to specify a size "0" in the device-tree to mean
> "the remainder". This patch makes u-boot compatible with the kernel's
> MTD parti
The Successive Approximation ADC (SARADC) in RK3528 uses the v2
controller and support:
- 10-bit resolution
- Up to 1MS/s sampling rate
- 4 single-ended input channels
- Current consumption: 0.5mA @ 1MS/s
Add support for the 4 channels of 10-bit resolution supported by SARADC
in RK3528.
Signed-of
From: Yao Zi
Add missing clocks in UART nodes for RK3528 SoC.
Signed-off-by: Yao Zi
Link: https://lore.kernel.org/r/20250217061142.38480-10-zi...@disroot.org
Signed-off-by: Heiko Stuebner
[ upstream commit: b9454434d0349223418f74fbfa7b902104da9bc5 ]
(cherry picked from commit 12f69f638472dc9
On Allwinner boards we use the first few words of the SID efuse storage
to generate a serial number, and also MAC addresses for Ethernet and
WiFi interfaces.
On some SoCs (A64, at least), when they are using Secure Boot, the SID
device contains all zeroes when read from U-Boot, because we are runni
Add support for the OTP controller in RK3528. The OTPC is similar to the
OTPC in RK3568 and can use the same ops for reading OTP data.
Signed-off-by: Jonas Karlman
---
v2: New patch
---
drivers/misc/rockchip-otp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/misc/rockchip-otp.
From: Joseph Chen
Add clock driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Joseph Chen
Signed-off-by: Finley Xiao
Signed-off-by: Jonas Karlman
---
Changes in v2:
- Use mainline Linux dt-bindings headers and
Add initial support for SDHCI controller in RK3528.
Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
more work is needed to get the faster HS200/HS400/HS400ES modes working.
Variant tap and delay num is copied from vendor Linux tag
linux-6.1-stan-rkr5.
Signed-off-by: Jona
Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.
Add initial arch support for the RK3528 SoC.
Signed-off-by: Jonas Karlman
---
Changes in v2:
- Add FIREWALL_DDR handling to fix emmc/fspi/sdmmc/usb dma
- Add imply SYSRESET_PSCI if SPL_ATF
- Add USB_GADGET_PRODUCT_NUM for RK3528
- Dro
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the maskrom button using a adc-keys node, also add the
regulators used by SARADC controller.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250304201642.831218-5-jo...@kwiboo.se
Signed
The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB).
Enable support for the onboard eMMC on Radxa E20C.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250305214108.1327208-4-jo...@kwiboo.se
Signed-off-by: Heiko Stuebner
[ upstream commit: 3a01b5f14a8ae2d45ae
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
CH340B for debug console use.
Add pinctrl for UART0 M0 pins used for serial console.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250228064024.320-6-jo...@kwiboo.se
Signed-off-by: Heiko Stuebner
[ upstr
From: Chukun Pan
Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
Add SCMI clk for CPU, GPU and RNG will also use it.
Signed-off-by: Chukun Pan
Link: https://lore.kernel.org/r/2025030718.789129-2-amad...@jmu.edu.cn
Signed-off-by: Heiko Stuebner
[ upstream commit: fbcbc1fb93e14729bd
From: Chukun Pan
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Signed-off-by: Chukun Pan
Link: https://lore.kernel.org/r/20250306123809.273655-3-amad...@jmu.edu.cn
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
Signed-off-by: Jonas Karlman
Link: https://lore.kernel.org/r/20250228064024.320-5-jo...
From: Yao Zi
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Signed-off-by: Yao Zi
Link: https://lore.kernel.org/r/20250217061142.38480-9-zi...@disroot.org
Signed-off-by: Heiko S
Hi Tom,
On Mon, 7 Apr 2025 at 12:22, Tom Rini wrote:
>
> On Mon, Apr 07, 2025 at 09:24:16AM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Mon, 7 Apr 2025 at 08:31, Tom Rini wrote:
> > >
> > > On Mon, Apr 07, 2025 at 12:35:15PM +1200, Simon Glass wrote:
> > > > Hi Tom,
> > > >
> > > > On Mon,
On Mon, Apr 07, 2025 at 08:44:23AM +0200, Heinrich Schuchardt wrote:
> Since commit 53d5a221632e ("emulation: Use bloblist to hold tables")
> `make qemu-riscv64_smode_defconfig acpi.config && make` fails with
>
> qfw_acpi.c:146:(.text.evt_write_acpi_tables+0xc):
> undefined reference to `
Enable Airoha SNFI SPI config to enable support for SNAND flash.
Signed-off-by: Christian Marangi
---
configs/an7581_evb_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
index fa41a4bca97..c74247e13db 100644
--- a/configs/a
Hi Tom,
On Mon, 7 Apr 2025 at 13:15, Tom Rini wrote:
>
> On Mon, Apr 07, 2025 at 09:18:12AM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Mon, 7 Apr 2025 at 07:53, Tom Rini wrote:
> > >
> > > On Mon, Apr 07, 2025 at 01:07:34PM +1200, Simon Glass wrote:
> > > > Hi Tom,
> > > >
> > > > On Mon,
On April 6, 2025 thus sayeth Daniel Schultz:
> Labels are not allowed before declarations. Add a semicolon after the
> label to introduce an empty statement. This will fix following error:
>
> arch/arm/mach-k3/common_fdt.c: In function 'fdt_fixup_reserved':
> arch/arm/mach-k3/common_fdt.c:156:2:
A common device attached to SPI are SPI NAND and some device might
require to have info on the attached NAND to know the flash page size
and spare size.
To support this, introduce setup_for_spinand() that pass the attached
spinand info from manufacturer.
Signed-off-by: Christian Marangi
---
inc
Add SNAND node to Airoha AN7581 EVB DTS to enable support for attached
SNAND flash.
Signed-off-by: Christian Marangi
---
arch/arm/dts/an7581-u-boot.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi
ind
Call SPI setup_for_spinand() if supported and defined to configure the
SPI slave for the attached NAND. This is needed to configure the SPI
with the NAND page size and spare size for correct configuration of the
device.
Call it as soon as the NAND is detected to correctly handle SPI
controller wit
Port Linux kernel regmap_set/clear_bits shorthands to set and clear bits
in a regmap. These are handy if only specific bits needs to be applied
or cleared and makes it easier to port regmap based driver from kernel
upstream.
Signed-off-by: Christian Marangi
---
include/regmap.h | 28
Add Ethrnet config to defconfig to enable Ethernet support.
Signed-off-by: Christian Marangi
---
configs/an7581_evb_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
index f09b5b603a2..f5bd647cb6e 100644
--- a/configs/an7581
Add Ethrnet nodes for Airoha AN7581 EVB board.
Signed-off-by: Christian Marangi
---
arch/arm/dts/an7581-u-boot.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi
index 9f8abfc3bcf..a569044195d
Add airoha Ethernet driver for Airoha AN7581 SoC. This is a majorly
rewritten and simplified version of the Linux airoha_eth.c driver.
It's has been modified to support a single RX/TX ring to reflect U-Boot
implementation with recv and send API.
The struct and the define are kept as similar as po
Add pending Chip SCU node for clock node.
Signed-off-by: Christian Marangi
---
arch/arm/dts/an7581-u-boot.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi
index 0316b73f3a5..9f8abfc3bcf 100644
--- a/arch/arm/dts/an7
This is continuation of the initial patchset for airoha
support.
Some are trivial fix for spi.
A new concept to setup SPI from detected NAND.
Sadly DTS node still need to be merged upstream so we
are currently adding them to u-boot dtsi and it's planned
to be dropped once they are accepted in ups
Hi Fabio
On Mon, Apr 7, 2025 at 9:55 PM Christian Marangi
wrote:
> On Sat, Mar 15, 2025 at 10:24:14AM +0100, Christian Marangi wrote:
> > It's currently possible to make the bootloader crash on calling
> > clk_set_rate caused by the loop in clk_clean_rate_cache.
> >
> > The loop assume that ever
(u64)switch_to_el1, ES_TO_AARCH64);
---
base-commit: 848f7ffc64aa7c4cc2229095812625c12343c8c1
change-id: 20250407-el1-boot-792926ba6090
Best regards,
--
George Chan
From: Vitor Soares
Add support for the Toradex SMARC iMX8MP.
Link:
https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx-8m-plus
Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit
Signed-off-by: Vitor Soares
---
The support for the Linux Kernel has
Hi,
On 2025/03/22 1:58, biguncle...@gmail.com wrote:
From: Maksim Kiselev
Hello everyone!
I've encountered an issue where the actual length of received data is
calculated incorrectly in the case of a multiple TRB request.
Below, I'll try to describe the essence of the problem:
A USB-etherne
Currently the msm_sdhci doesn't yet support DLL configurations which are
required to enable bus speeds greater that 100MHz. So disable HS200 mode
support as of now as it requires bus speeds of 200MHz.
This should fix eMMC issues reported on RB1.
Signed-off-by: Sumit Garg
---
configs/qcom_defcon
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