On 7/27/21 4:54 AM, Zong Li wrote:
Invokes the generic cache_enable interface to execute the relative
implementation in SiFive ccache driver.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu540/Kconfig | 1 +
arch/riscv/cpu/fu540/cache.c | 62 ---
On 7/27/21 4:54 AM, Zong Li wrote:
This driver is currently responsible for enabling all ccache ways.
Can you expand on this a little? Perhaps describe the hardware a little. For
example,
you could describe what a way/bank is, and that they can't be disabled by the
hardware.
Signed-off-by:
If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.
Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used in
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.
This may potentially create an inconsistent config where the 2 values
do not match. Let's use
Hi Tim,
On Mon, 26 Jul 2021 at 12:42, Tim Harvey wrote:
>
> On Sat, Jul 24, 2021 at 3:01 PM Simon Glass wrote:
> >
> > Hi Tim,
> >
> > On Fri, 23 Jul 2021 at 16:52, Tim Harvey wrote:
> > >
> > > On Fri, Jul 23, 2021 at 2:41 PM Simon Glass wrote:
> > > >
> > > > Hi Tim,
> > > >
> > > > On Fri,
Hi Tim,
On Mon, 26 Jul 2021 at 12:20, Tim Harvey wrote:
>
> On Sun, Jul 25, 2021 at 9:54 AM Simon Glass wrote:
> >
> > This symbol is needed for binman to locate the start of the image. Add it.
> >
> > Note: the existing line to bring in the .__image_copy_start symbol does
> > not appear to do a
The common TI SCI header file uses some macros from err.h and these
get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include
the linux/err.h header file in this header file directly rather
than relying on source files to include it to eliminate any
potential build errors.
While at this, r
Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.
Signed-off-by: Suman Anna
---
arch/arm/mach-k3/common.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/
Hi Lokesh,
The following are two minor cleanups/fixes that I ran into
while doing some development work on a newer SoC due to
different Kconfig symbols.
Following is the patch summary:
- Patch #1 makes the ti_sci_protocol.h self-contained
when CONFIG_TI_SCI_PROTOCOL is not defined.
- Patch
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- LTE CAT M1 modem
- USB 2.0 HUB
- M.2 Socket with USB2.0, PCIe, and dual-SIM
- IMX8M FEC
- PCIe based GbE
- RS232/RS485/RS422 serial transceiver
- GPS
- CAN bus
- WiFi / Bluetooth
Add the specific board model from EEPROM config to the device-tree to
make it easier to access from Linux userspace.
Signed-off-by: Tim Harvey
---
board/gateworks/venice/imx8mm_venice.c | 8
configs/imx8mm_venice_defconfig| 1 +
2 files changed, 9 insertions(+)
diff --git a/boa
Add board model/serial# strings to env. Move the creation of the strings
to gsc_read() and the display of the info into gsc_info() so they are
available to U-Boot proper.
Signed-off-by: Tim Harvey
---
board/gateworks/venice/gsc.c | 67 ++
board/gateworks/venice/
replace looking up i2c bus name by bus number and define bus numbers and
eeprom address with #defines.
Signed-off-by: Tim Harvey
---
board/gateworks/venice/gsc.c | 19 ++-
board/gateworks/venice/gsc.h | 5 +
board/gateworks/venice/spl.c | 4 ++--
3 files changed, 17 inserti
Get mem size from dt which SPL updated per EEPROM config.
Signed-off-by: Tim Harvey
---
board/gateworks/venice/imx8mm_venice.c | 28 +-
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/board/gateworks/venice/imx8mm_venice.c
b/board/gateworks/venice/imx8mm_
Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties
not supported by U-Boot drivers/net/phy/dp83867.c with the proper
'ti,fifo-depth' property.
Signed-off-by: Tim Harvey
---
arch/arm/dts/imx8mm-venice-gw700x.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --g
Use the common imx8mm-u-boot.dtsi
Signed-off-by: Tim Harvey
---
arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi | 35 +--
1 file changed, 1 insertion(+), 34 deletions(-)
diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
ind
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12
is the power-enable to the TPS25821 Source controller and power switch
responsible for monitoring the CC pins and enabling VBUS. Therefore
GPIO1_12 must always be enabled and the vbus output enable from the
IMX8MM can be ignored
remove unused SPL features to shink the size of the SPL which
otherwise would no longer fit into IMX8M Mini OCRAM.
Signed-off-by: Tim Harvey
---
configs/imx8mm_venice_defconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the
Hi Lokesh,
The following patches fix the clock parenting of couple of post-divider
PLL output clocks for Main PLL0 and PLL1 on both J721E and J7200 SoCs.
The Main PLL1 register values are also fixed up (they were pointing to
PLL0 atm).
These PLL POSTDIV clocks are in sequence and the last POSTDI
On Tue, Jul 27, 2021 at 12:17 PM Heiko Thiery wrote:
>
> Hi all,
>
> Am Mi., 5. Mai 2021 um 15:30 Uhr schrieb ZHIZHIKIN Andrey
> :
> >
> > Hello Oliver,
> >
> > > -Original Message-
> > > From: U-Boot On Behalf Of Oliver Graute
> > > Sent: Wednesday, May 5, 2021 2:01 PM
> > > To: sba...@d
Hi Alex,
Am Di., 27. Juli 2021 um 16:34 Uhr schrieb Alex G. :
>
>
>
> On 7/27/21 4:59 AM, Heiko Thiery wrote:
> > Hi all,
> >
> > Am Do., 15. Juli 2021 um 00:09 Uhr schrieb Alexandru Gagniuc
> > :
> >>
> >> Host tool features, such as mkimage's ability to sign FIT images were
> >> enabled or disab
Hi all,
Am Mi., 5. Mai 2021 um 15:30 Uhr schrieb ZHIZHIKIN Andrey
:
>
> Hello Oliver,
>
> > -Original Message-
> > From: U-Boot On Behalf Of Oliver Graute
> > Sent: Wednesday, May 5, 2021 2:01 PM
> > To: sba...@denx.de
> > Cc: feste...@gmail.com; peng@nxp.com;
> > oliver.gra...@kococo
t-amlogic/pipelines/8444
>
> Thanks,
> Neil
>
> The following changes since commit b70b9b07463db2f6937c7ea6d7fb5122feb7ba1b:
>
> Prepare v2021.10-rc1 (2021-07-26 20:57:18 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/cust
Start out by documenting general expectations on when CI is run, how
anyone can run Azure pipelines, and how GitLab CI pipelines can be run.
Signed-off-by: Tom Rini
---
Changes in v3:
- Really address all of the feedback.
Changes in v2:
- Address some of Akashi-san's feedback
---
doc/develop/ci
Start out by documenting general expectations on when CI is run, how
anyone can run Azure pipelines, and how GitLab CI pipelines can be run.
Signed-off-by: Tom Rini
---
Changes in v2:
- Address some of Akashi-san's feedback
---
doc/develop/ci_testing.rst | 45
The previously mentioned commit didn't resolve the issue. When testing I
made a mistake.
The workaround I'm using to resolve the issue is by disabling the DDR mode
juste before re-init happens (DDR mode will be automatically enabled later
in the init process).
Now I don't know if this is really a
Hi Tom,
On Sun, 11 Jul 2021 at 20:19, Simon Glass wrote:
>
> U-Boot provides a verified-boot feature based around FIT, but there is
> no standard way of implementing it for a board. At present the various
> required pieces must be built up separately, to produce a working
> implementation. In par
On Tue, Jul 27, 2021 at 11:22:31AM +0200, Patrick DELAUNAY wrote:
> Hi Tom,
>
> Please pull the STM32 related patches for u-boot/master, v2021.10:
> u-boot-stm32-20210727
>
> - FIP Enable OP-TEE and TZC support in SPL for STM32MP15 SoC
> - Add stm32mp15 missing SPI clock su
b70b9b07463db2f6937c7ea6d7fb5122feb7ba1b:
Prepare v2021.10-rc1 (2021-07-26 20:57:18 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
tags/u-boot-amlogic-20210727
for you to fetch changes up to 24d2aea19b8069fb124313435cffcbb07c8317a1:
configs: Enable SMBIOS for
These 2 options are no longer needed as now binman is used to build
u-boot.rom.
Signed-off-by: Bin Meng
---
Kconfig| 21 -
arch/x86/Kconfig | 2 --
arch/x86/cpu/quark/Kconfig | 1 -
doc/arch/x86.rst | 13 ++---
4 files change
On Mon, Jul 26, 2021 at 11:26:39PM -0400, Sean Anderson wrote:
> On 7/26/21 10:52 PM, Tom Rini wrote:
> > - Forwarded message from scan-ad...@coverity.com -
> >
> > Date: Tue, 27 Jul 2021 01:10:27 + (UTC)
> > From: scan-ad...@coverity.com
> > To: tom.r...@gmail.com
> > Subject: New Def
The Hitachi tx18d42vm LCD panel driver is really just initialising the
device, using bitbanged SPI, during operation there is nothing to do.
This makes the driver self contained, so drop the bogus dependency on
the legacy CONFIG_VIDEO.
This avoids the warning when building Chuwi_V7_CW0825_defconfi
On 7/27/21 4:59 AM, Heiko Thiery wrote:
Hi all,
Am Do., 15. Juli 2021 um 00:09 Uhr schrieb Alexandru Gagniuc
:
Host tool features, such as mkimage's ability to sign FIT images were
enabled or disabled based on the target configuration. However, this
misses the point of a target-agnostic hos
On 7/27/21 4:15 AM, Damien Le Moal wrote:
On 2021/07/27 12:51, Sean Anderson wrote:
Some clock functions return ulong but still have "negative" errors. To deal
with this, cast the relevant arguments to long.
Fixes: 609bd60b94 ("clk: k210: Rewrite to remove CCF")
Reported-by: Coverity Scan
Sign
binman complains when binary blobs are present:
Node '/binman/rom/intel-vga': Offset 0xfff9 (4294508544) overlaps
with previous entry '/binman/rom/u-boot-dtb-with-ucode' ending at
0xfff9204c (4294516812)
Adjust VGA rom address to 0xfffa so that u-boot.rom image can be
successfully b
Hi Jaehoon,
yes, DDR mode works fine before executing "mmc dev 2" command.
However, for "mmc rescan" command or "mmc info" to work, I need to first
select the correct mmc device using the "mmc dev 2" command, cuz the
default one is device 0 in my case which is empty.
OTOH, after hours of debugging
On Tue, Jul 27, 2021 at 05:42:51AM +, Z.Q. Hou wrote:
> Hi Tom,
>
> > -Original Message-
> > From: Tom Rini
> > Sent: 2021年7月26日 20:29
> > To: Z.Q. Hou
> > Cc: Michael Walle ; Heinrich Schuchardt
> > ; u-boot@lists.denx.de; Priyanka Jain
> >
> > Subject: Re: [PATCH] configs: layersc
Reviewed-by: Jaehoon Chung
Sorry, Forgot to add Reviewed-by:
https://patchwork.ozlabs.org/project/uboot/patch/20210724081009.15761-8-ashok.reddy.s...@xilinx.com/
Thanks,
Ashok
> -Original Message-
> From: Ashok Reddy Soma
> Sent: Tuesday, July 27, 2021 6:07 PM
> To: u-boot@lists.denx
Reviewed-by: Jaehoon Chung
Sorry, Forgot to add Reviewed-by:
https://patchwork.ozlabs.org/project/uboot/patch/20210724081009.15761-6-ashok.reddy.s...@xilinx.com/
Thanks,
Ashok
> -Original Message-
> From: Ashok Reddy Soma
> Sent: Tuesday, July 27, 2021 6:07 PM
> To: u-boot@lists.denx
Reviewed-by: Jaehoon Chung
Sorry, Forgot to add Reviewed-by:
https://patchwork.ozlabs.org/project/uboot/patch/20210724081009.15761-5-ashok.reddy.s...@xilinx.com/
Thanks,
Ashok
> -Original Message-
> From: Ashok Reddy Soma
> Sent: Tuesday, July 27, 2021 6:07 PM
> To: u-boot@lists.den
tap_delays.c just has calls to xilinx_pm_request() for setting tapdelays.
Simply move these calls to zynq_sdhci.c and make them static inline.
Similarly zynqmp_tap_delay.h also has call to xilinx_pm_request() for
dll reset. Do the same for this file as well.
Remove tap_delays.c and zynqmp_tap_dela
From: T Karthik Reddy
As per SD spec when SD host controller is reset, it takes 1000msec
to detect the card state. In case, if we enable the sd bus voltage &
card detect state is not stable, then host controller will disable
the sd bus voltage.
In case of warm/subsystem reboot, due to unstable c
Change return type of arasan_sdhci_set_tapdelay() to int, to facilitate
returning errors. Get return values from input and output set clock phase
functions inside arasan_sdhci_set_tapdelay() and return those errors.
Signed-off-by: T Karthik Reddy
Signed-off-by: Ashok Reddy Soma
---
Changes in v
Since set_control_reg is available in sdhci.c, use it and remove
arasan_sdhci_set_control_reg().
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
drivers/mmc/zynq_sdhci.c | 21 +
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c
Currently xilinx sdhci driver is using zynqmp_mmio_write() to set
tapdelay values. Use xilinx_pm_request() using appropriate arguments
to set input/output tapdelays for zynqmp. Where tapdelay setting is
done by firmware. Host driver should explicitly request DLL reset
before ITAP (assert DLL) and a
From: T Karthik Reddy
Add enums for pm node id's, pm ioctl id's, tapdelay types, dll reset types
Signed-off-by: T Karthik Reddy
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
include/zynqmp_firmware.h | 127 ++
1 file changed, 127 insertions(+)
Change deviceid to node_id in arasan_zynqmp_dll_reset() and also in
tapdelay related static inline functions to reflect proper name and
for consistency.
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
drivers/mmc/zynq_sdhci.c | 14 +++---
1 file changed, 7 insertions(+), 7 de
This patch series updates/fixes below things:
- Handle errors from tapdelay functions and return to set_delay()
- Add ZynqMP firmware related enums which are used in sdhci driver
- Replace mmio_write() with firmware call xilinx_pm_request()
- Move tapdelay setting code from tap_delays.c to driv
set_delay() has return type as void. If there are any errors while
setting tapdelay's it won't be able to return them.
Change the prototype of set_delay() in sdhci_ops structure and return
the errors from wherever it is called.
Signed-off-by: Ashok Reddy Soma
---
Changes in v2:
- This is the s
Andre,
On 7/27/21 7:12 AM, Andre Przywara wrote:
> On Sun, 18 Apr 2021 22:21:41 -0500
> Samuel Holland wrote:
>
> Hi,
>
>> Most sun6i-derived SoCs contain SRAM A2, a secure SRAM area for ARISC
>> SCP firmware. H3 has a smaller SRAM than other SoCs (A31/A33/A23/A83T).
>>
>> On sun8i SoCs which d
On Sun, 18 Apr 2021 22:21:41 -0500
Samuel Holland wrote:
Hi,
> Most sun6i-derived SoCs contain SRAM A2, a secure SRAM area for ARISC
> SCP firmware. H3 has a smaller SRAM than other SoCs (A31/A33/A23/A83T).
>
> On sun8i SoCs which do not have SRAM B, we can use part of this SRAM for
> the secur
On 2021/07/27 12:51, Sean Anderson wrote:
> Some clock functions return ulong but still have "negative" errors. To deal
> with this, cast the relevant arguments to long.
>
> Fixes: 609bd60b94 ("clk: k210: Rewrite to remove CCF")
> Reported-by: Coverity Scan
> Signed-off-by: Sean Anderson
> ---
>
Hi everyone. I have a boot problem on the imx28 board, the problem
repeats with kernels 4.14.67 and 5.10.50, so I decided to ask on the
u-boot mailing list as I think the problem is not kernel related, but
related to u-boot variables.
i have the following u-boot variables in boot.scr:
setenv mtdpa
I am attempting to use mkimage to build a uImage for a new architecture:
csky. This architecture is already in the mainline kernel.
It appears the only thing to do is to added a new enumeration after
IH_ARCH_RISCV in u-boot/include/image.h and to add a corresponding entry
into uimage_arch in u-boo
Device tree alignment with Linux kernel v5.14-rc3
- ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15
- ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151
- ARM: dts: stm32: add a new DCMI pins group on stm32mp15
- ARM: dts: stm32: fix ltdc pinctrl on microd
Hi all,
Am Do., 15. Juli 2021 um 00:09 Uhr schrieb Alexandru Gagniuc
:
>
> Host tool features, such as mkimage's ability to sign FIT images were
> enabled or disabled based on the target configuration. However, this
> misses the point of a target-agnostic host tool.
>
> A target's ability to verif
On 7/24/21 5:35 PM, Heinrich Schuchardt wrote:
CONFIG_HEXDUMP is needed to display UEFI variables using 'printenv -e'.
Enabling CONFIG_SPL_HEXDUMP only makes sense for debugging purposes.
Hence CONFIG_SPL_HEXDUMP should not be enabled by default.
The following boards currently have CONFIG_SPL
Hi Tom,
Please pull the STM32 related patches for u-boot/master, v2021.10:
u-boot-stm32-20210727
- FIP Enable OP-TEE and TZC support in SPL for STM32MP15 SoC
- Add stm32mp15 missing SPI clock support
- Manage pull-up on gpio button STM32MP15 boards
- Correct STM32MP15 boot when TAMPER
Hi,
On 7/15/21 9:19 PM, Alexandru Gagniuc wrote:
Add the "/reserved-memory/optee" node to the SPL devicetree. The
purpose is to allow configuring TZC regions when booting OP-TEE.
Signed-off-by: Alexandru Gagniuc
Reviewed-by: Simon Glass
---
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 +++
hI,
On 7/15/21 9:19 PM, Alexandru Gagniuc wrote:
OP-TEE is very particular about how the TZC should be configured.
When booting an OP-TEE payload, an incorrect TZC configuration will
result in a panic.
Most information can be derived from the SPL devicetree. The only
information we don't have i
Hi,
On 7/15/21 9:19 PM, Alexandru Gagniuc wrote:
The purpose of this change is to allow configuring TrustZone (TZC)
memory permissions. For example, OP-TEE expects TZC regions to be
configured in a very particular way. The API presented here is
intended to allow exactly that.
UCLASS support is
Hi,
On 7/15/21 9:19 PM, Alexandru Gagniuc wrote:
OP-TEE requires some particular setup, which is not needed for linux
or other payloads. Add a hook for platform-specific code to perform
any OP-TEE related configuration and initialization.
A weak function is used because it is symmetrical to oth
Modify command line arguments at mkeficapsule as the syntax was
a bit modified in the previous commit.
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_capsule/conftest.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/test/py/tests/test_efi_capsule/conftest
The existing options, "--fit" and "--raw," are only used to put a proper
GUID in a capsule header, where GUID identifies a particular FMP (Firmware
Management Protocol) driver which then would handle the firmware binary in
a capsule. In fact, mkeficapsule does the exact same job in creating
a capsu
To run efi capsule authentication test in CI loop, U-Boot binary must be
compiled with an appropriate public key (esl file).
Add a rule to build this binary with sandbox_capsule_auth_defconfig
and run the test.
Signed-off-by: AKASHI Takahiro
---
.gitlab-ci.yml | 6 ++
1 file changed, 6 inser
This new configuration, which was derived from sandbox_defconfig, will be
used solely to run efi capsule authentication test as the test requires
a public key (esl file) to be embedded in U-Boot binary.
Signed-off-by: AKASHI Takahiro
---
configs/sandbox_capsule_auth_defconfig | 307 +
Add a couple of test cases against capsule image authentication
for capsule-on-disk, where only a signed capsule file with the verified
signature will be applied to the system.
Due to the difficulty of embedding a public key (esl file) in U-Boot
binary during pytest setup time, all the keys/certif
The check for CONFIG_EFI_CAPSULE_KEY_PATH:
ifeq ("$(wildcard $(EFI_CAPSULE_KEY_PATH))","")
does not allow users to specify a relative path for including a public
key binary. This is fine for most of all cases, but it will make it
difficult to add pytest test cases as pre-created keys/certificat
Hi,
On 7/15/21 9:19 PM, Alexandru Gagniuc wrote:
In general, Falcon mode means we're booting a linux kernel directly.
With FIT images, however, an OP-TEE secure kernel can be booted before
linux. Thus, if the next stage is an IH_OS_TEE, this isn't necessarily
a problem.
Of course, a general sol
Add a man page for mkeficapsule command.
Signed-off-by: AKASHI Takahiro
---
MAINTAINERS| 1 +
doc/mkeficapsule.1 | 91 ++
2 files changed, 92 insertions(+)
create mode 100644 doc/mkeficapsule.1
diff --git a/MAINTAINERS b/MAINTAINERS
index ae
Now we can use mkeficapsule command instead of EDK-II's script
to create a signed capsule file. So update the instruction for
capsule authentication.
Signed-off-by: AKASHI Takahiro
---
doc/develop/uefi/uefi.rst | 31 ++-
1 file changed, 14 insertions(+), 17 deletions(
With this enhancement, mkeficapsule will be able to sign a capsule
file when it is created. A signature added will be used later
in the verification at FMP's SetImage() call.
To do that, We need specify additional command parameters:
-monotonic-cout : monotonic count
-private-key : private k
As I proposed and discussed in [1] and [2], I have made a couple of
improvements on the current implementation of capsule update in this
patch set.
* add signing feature to mkeficapsule
* add "--guid" option to mkeficapsule
* add man page of mkeficapsule
* add pytest for capsule authentication (on
Hi,
On 7/20/21 11:46 PM, Marek Vasut wrote:
Commit 500327e2ea7 ("ARM: dts: stm32mp1: DT alignment with Linux kernel
v5.8-rc1")
renamed sdmmc2_d47_pins_b phandle to sdmmc2_d47_pins_c, but without updating
the AV96 DT which uses that phandle. Linux missed similar update as well and
it was only ad
Hi,
On 7/9/21 2:24 PM, Patrick Delaunay wrote:
Add the missing SPI clock even if these instances are not available
on STMicroelectronics boards: SPI2_K, SPI3_K, SPI4_K, SPI6_K.
With this patch, the SPI2 / SPI3 / SPI4 / SPI6 instances can be used on
customer design without the clock driver error
Hi,
On 7/9/21 9:53 AM, Patrick Delaunay wrote:
When a push-button is released and PA13/PA14 are defined as input (high-Z)
the LED should not be active as the circuit is open but a small current
leak through PCB or push-button close the circuit and allows a small LED
bias giving erroneous level v
Hi,
On 7/8/21 10:53 AM, Patrick Delaunay wrote:
When the TAMP register 20 have an invalid value (0x0 for example after
TAMPER error) the "boot_device" U-Boot env variable have no value and
no error is displayed in U-Boot log.
The STM32MP boot command bootcmd_stm32mp failed with strange trace:
Hi,
On 7/8/21 10:53 AM, Patrick Delaunay wrote:
When the TAMP register 20 have an invalid value (0x0 for example after
TAMPER error) the "boot_device" U-Boot env variable have no value and
no error is displayed in U-Boot log.
The STM32MP boot command bootcmd_stm32mp failed with strange trace:
Add board_fdt_blob_setup to return the device tree location which is
passed by prior stage in u-boot proper. The generic board_fdt_blob_setup
always returns _end, it mignt be ok because u-boot SPL would currently
put the dtb there, but it would be broken if we put the dtb to another
place and assig
As (3581811dc26f "riscv: sifive/fu540: Move SPL related functions to spl.c"),
we put the SPL stuff in spl.c, we don't need to compile unleashed.c and
unmatched.c in SPL build.
Signed-off-by: Zong Li
---
board/sifive/unleashed/Makefile | 4 ++--
board/sifive/unmatched/Makefile | 3 ++-
2 files ch
Invokes the generic cache_enable interface to execute the relative
implementation in SiFive ccache driver.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu540/Kconfig | 1 +
arch/riscv/cpu/fu540/cache.c | 62 ---
arch/riscv/cpu/fu740/Kconfig
This driver is currently responsible for enabling all ccache ways.
Signed-off-by: Zong Li
---
drivers/cache/Kconfig | 7 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-sifive-ccache.c | 69 +
3 files changed, 77 insertions(+)
creat
On 14/05/2021 22:54, Alper Nebi Yasak wrote:
> With commit 84a42ae36683 ("dm: core: Rename device node to indicate it
> is private") and commit f10643cf8a4c ("dm: core: Access device ofnode
> through functions") accesses to the "node" member were replaced with
> dev_ofnode(). Also apply that replac
On 14/05/2021 22:54, Alper Nebi Yasak wrote:
> With commit 41575d8e4c33 ("dm: treewide: Rename auto_alloc_size members
> to be shorter") "priv_auto_alloc_size" was renamed to "priv_auto". Apply
> the rename to these two drivers as well.
>
> Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Anal
On 27/07/2021 03:23, Artem Lapkin wrote:
> Enable configs to support SMBIOS for all Khadas VIM boards
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Artem Lapkin
> ---
> configs/khadas-vim2_defconfig | 2 ++
> configs/khadas-vim3_defconfig | 2 ++
> configs/khadas-vim3l_defconfig | 2 ++
>
On 27/07/2021 03:23, Artem Lapkin wrote:
> Khadas vim series: Use devicetree for SMBIOS settings
> Add settings and enable the default sysinfo driver so that these can come
> from the device tree.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Artem Lapkin
> ---
> .../meson-g12b-a311d-khadas-
On 27/05/2021 08:43, Artem Lapkin wrote:
> make possible to load simple compressed linux kernel for meson64
>
> Signed-off-by: Artem Lapkin
> ---
> include/configs/meson64.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/configs/meson64.h b/include/configs/meson64.h
> index
On 13/07/2021 08:48, Artem Lapkin wrote:
> phy-names was improperly implemented resulting in an inoperable USB-OTG
> port.
>
> - phy-names = "usb2-phy0\0\0usb2-phy1\0";
> + phy-names = "usb2-phy0\0usb2-phy1";
>
> Signed-off-by: Artem Lapkin
> ---
> board/amlogic/vim3/vim3.c | 4 ++--
> 1 file c
Hi Alexandru,
On 5/17/21 8:39 PM, Alexandru Gagniuc wrote:
This test verifies that ECDSA_UCLASS is implemented, and that
ecdsa_verify() works as expected. The definition of "expected" is
"does not find a device, and returns -ENODEV".
The lack of a hardware-independent ECDSA implementation preve
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