Hi All
Since patch also reviewed by Jaehoon, how about merge it into mainline?
Best Regards
Andy Wu
> -Original Message-
> From: Jaehoon Chung
> Sent: Thursday, May 20, 2021 6:03 AM
> To: Wu, Andy ; peng@nxp.com;
> jh80.ch...@gmail.com; u-boot@lists.denx.de
> Cc: CPGS
> Subject: Re
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis,
spis, ttcs, uarts, watchdog that's why make sense to also enable access to
change this clock. For this clock you already get the rate.
Signed-off-by: Michal Simek
---
drivers/clk/clk_zynqmp.c | 1 +
1 file changed, 1 in
LS1043A-QDS board requires updation in few environment configs in TFA
and QSPI defconfigs.
Following are the changes:
- Define CONFIG_ENV_ADDR
- Unset CONFIG_SPI_FLASH_BAR
- Enable CONFIG_SYS_RELOC_GD_ENV_ADDR
Signed-off-by: Kuldeep Singh
---
configs/ls1043aqds_qspi_defconfig| 1 +
Hi Tianrui,
On Wed, Jul 07, 2021 at 12:02:00PM +0800, Tianrui Wei wrote:
> Previous device tree for OpenPitonemits a warning during compilation,
typo: OpenPiton emits ?
> thus was rejected by Tom. This commit fixes the previous warning and
Tom has actually accepted the patch, so this line could
From: Piyush Mehta
The board zynqmp-zc1751-xm016-dc2 support only USB2.0.
This patch removes USB3.0 DT configuration for DC2 board.
Signed-off-by: Piyush Mehta
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/a
Hi Ricardo,
On 07/07/21 4:39 am, Ricardo Salveti wrote:
> Hi Aswath,
>
> On Thu, Mar 25, 2021 at 4:19 AM Aswath Govindraju wrote:
>>
>> First check if there is an alias for the device tree node defined with the
>> given num before checking against device index.
>>
>> Signed-off-by: Aswath Govind
On Tue, Jul 6, 2021 at 5:54 PM Teresa Remmet wrote:
>
> Hello Jagan,
>
> Am Montag, den 05.07.2021, 11:01 +0530 schrieb Jagan Teki:
> > On Fri, Jul 2, 2021 at 4:49 PM Teresa Remmet
> > wrote:
> > > Use now binman for image creation.
> > >
> > > Signed-off-by: Teresa Remmet
> > > ---
> > > .../i
Hi Tom, Leo,
Apologies for making that mistake, and many many thanks for merging our
patches! We’ve already fixed the problem with another patch.
Many thanks,
Tianrui
-Original Message-
From: Tom Rini
Date: Wednesday, July 7, 2021 at 3:52 AM
To: Leo Liang
Cc: u-boot@lists.denx.de , r.
Previous device tree for OpenPitonemits a warning during compilation,
thus was rejected by Tom. This commit fixes the previous warning and
adds dts to the OpenPiton RISC-V board and added the device tree to
MAINTAINER file.
Signed-off-by: Tianrui Wei
Reported-by: Tom Rini
---
arch/riscv/dts/ope
Am 7. Juli 2021 05:18:20 MESZ schrieb Heinrich Schuchardt :
>Am 7. Juli 2021 03:44:35 MESZ schrieb AKASHI Takahiro
>:
>>François,
>>
>>On Tue, Jul 06, 2021 at 08:10:08PM +0200, Heinrich Schuchardt wrote:
>>> On 7/6/21 6:13 PM, François Ozog wrote:
>>> > Hi Heinrich, U-Boot 2021-07rc5 does not take
Am 7. Juli 2021 05:18:20 MESZ schrieb Heinrich Schuchardt :
>Am 7. Juli 2021 03:44:35 MESZ schrieb AKASHI Takahiro
>:
>>François,
>>
>>On Tue, Jul 06, 2021 at 08:10:08PM +0200, Heinrich Schuchardt wrote:
>>> On 7/6/21 6:13 PM, François Ozog wrote:
>>> > Hi Heinrich, U-Boot 2021-07rc5 does not take
On Wed, Jun 30, 2021 at 09:31:34PM +0800, Jon Lin wrote:
> From: Chris Morgan
>
> Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
> this chip uses a continuation code which I cannot seem to parse, so
> there are possibly going to be collisions with chips that use the same
> ma
On Wed, Jun 30, 2021 at 09:31:31PM +0800, Jon Lin wrote:
> From: Chris Morgan
>
> This patch adds support for the Rockchip serial flash controller
> found on the PX30 SoC. It should work for versions 3-5 of the SFC
> IP, however I am only able to test it on v3.
>
> This is adapted from the WIP S
Am 7. Juli 2021 03:44:35 MESZ schrieb AKASHI Takahiro
:
>François,
>
>On Tue, Jul 06, 2021 at 08:10:08PM +0200, Heinrich Schuchardt wrote:
>> On 7/6/21 6:13 PM, François Ozog wrote:
>> > Hi Heinrich, U-Boot 2021-07rc5 does not take into account memory
>> > description when using Qemu 5.2 NUMA conf
François,
On Tue, Jul 06, 2021 at 08:10:08PM +0200, Heinrich Schuchardt wrote:
> On 7/6/21 6:13 PM, François Ozog wrote:
> > Hi Heinrich, U-Boot 2021-07rc5 does not take into account memory
> > description when using Qemu 5.2 NUMA configuration to adapt memory map
> > (kernel_addr_r...):
> >
> >
commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading
images")' changed the way buffer allocation worked for SPL to a more
flexible method.
For xilinx zynqmp the 1MB buffer is not necessarily enough when dealing
with complex fit images (e.g. containing FPGA/TF-A/OP-TEE/U-Boot
prop
Hi Aswath,
On Thu, Mar 25, 2021 at 4:19 AM Aswath Govindraju wrote:
>
> First check if there is an alias for the device tree node defined with the
> given num before checking against device index.
>
> Signed-off-by: Aswath Govindraju
> Reviewed-by: Lokesh Vutla
> Reviewed-by: Jaehoon Chung
> -
Hi,
At present U-Boot avoids the concept of 'opening' a file. Being in a
bootloader environment, it is normally better to take the action
immediately and avoid any caching, for example, since there is no
background task to clean up afterwards.
Having said that, the concept of a file is quite usef
On Mon, Jun 28, 2021 at 10:40:09AM +0200, Stephan Gerhold wrote:
> At the moment, the U-Boot serial_msm driver does not initialize the
> UART_DM_DMEN register with the required value. Usually this does not
> cause any problems, because there is Qualcomm's LK bootloader running
> before U-Boot whic
On Sun, Jun 27, 2021 at 01:06:15PM +0200, Stephan Gerhold wrote:
> It looks like SD card detection is broken at the moment for DB410c.
> The eMMC is detected correctly, but the SD card is not.
>
> This is probably similar to the issue fixed in commit 850514740358
> ("mmc: msm_sdhci: Use mmc_of_pa
On Sun, Jun 20, 2021 at 10:34:35AM +0800, Sheep Sun wrote:
> Fix typo in clock-snapdragon.c
>
> Signed-off-by: Sheep Sun
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Sun, Jun 20, 2021 at 10:34:34AM +0800, Sheep Sun wrote:
> The GICC register used by u-boot is 0x0a20c000, which is actually a GICC
> for WCNSS, the WLAN processor. U-boot runs on the Application Processor,
> therefore it should use APCS GICC instead. Hence, correct it with APCS GICC
> register
On Thu, Jun 10, 2021 at 10:37:02PM -0400, Trevor Woerner wrote:
> There's nothing special or unique to the lpc32xx that requires its own config
> parameter for specifying the console uart index. Therefore instead of using
> the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the
>
On Fri, Jun 04, 2021 at 06:43:23PM +0900, Masami Hiramatsu wrote:
> Without this fix, scsi-scan will cause a synchronous abort
> when accessing ops->scan.
>
> Signed-off-by: Masami Hiramatsu
> Reviewed-by: Simon Glass
For the entire series, applied to u-boot/master, thanks!
--
Tom
signatur
On Fri, Jun 04, 2021 at 02:25:36PM +1200, Chris Packham wrote:
> Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on
> equivalent code in Broadcom's LDK 5.0.6.
>
> Signed-off-by: Chris Packham
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Sat, May 15, 2021 at 02:44:19PM +0200, Linus Walleij wrote:
> We didn't convert the Integrator to use DM for PCI in
> time, and we don't use it either so let's just drop
> PCI support from the Integrator.
>
> Signed-off-by: Linus Walleij
> Reviewed-by: Tom Rini
Applied to u-boot/master, tha
On Tue, May 11, 2021 at 02:18:02PM -0400, si...@writeme.com wrote:
> From: Sinan Akman
>
> Signed-off-by: Sinan Akman
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On 7/6/21 5:52 PM, Stephan Gerhold wrote:
> On Tue, Jul 06, 2021 at 10:08:03AM +0900, Jaehoon Chung wrote:
>> On 7/6/21 1:28 AM, Stephan Gerhold wrote:
>>> All devices based on ST-Ericsson Ux500 use a PMIC similar to AB8500
>>> (Analog Baseband). There is AB8500, AB8505, AB9540 and AB8540
>>> altho
On 7/6/21 6:11 PM, Tim Harvey wrote:
On Sun, Jul 4, 2021 at 12:25 PM Marek Vasut wrote:
On 7/4/21 5:35 PM, Fabio Estevam wrote:
Hi Marek,
Hi,
On Sat, Jul 3, 2021 at 10:04 PM Marek Vasut wrote:
Retrieving the USB base addresses from DT would be preferred, yes, but
the current code does
On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote:
> Hi Tom,
>
> The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
>
> Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
>
> are available in the Git repository at:
>
> g...@source.d
On Tue, Jul 06, 2021 at 10:41:44AM +0300, Ramon Fried wrote:
> Hi Tom,
>
> Please pull the latest patches in u-boot-net tree.
> It contains scattered commits to the network tree.
>
> The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
>
> Merge branch '2021-07-01-upda
On 7/6/21 12:11 PM, Maxime Ripard wrote:
On Tue, Jul 06, 2021 at 04:57:32PM +0100, Andre Przywara wrote:
On Tue, 6 Jul 2021 19:56:24 +0530
Jagan Teki wrote:
Hi Jagan,
thanks for the response!
> On Tue, Jul 6, 2021 at 4:53 AM Andre Przywara wrote:
> >
> > The ums command (presenting a U-B
On 7/6/21 6:13 PM, François Ozog wrote:
Hi Heinrich, U-Boot 2021-07rc5 does not take into account memory
description when using Qemu 5.2 NUMA configuration to adapt memory map
(kernel_addr_r...):
-smp 4 \
-m 8G,slots=2,maxmem=16G \
-object memory-backend-ram,size=4G,id
I have been working on an updated version, I have cleaned up the
config a lot as well as done some work to make the -u-boot.dtsi file
smaller
https://pagure.io/u-boot/c/2472db2eff8ba0fb262a0d0264aa9d9c7b3eca32?branch=helios64
is my current WIP patch, I have built it on top of updating the base
rk3
If reset-gpio is defined by device-tree use that if
CONFIG_PCIE_IMX_PERST_GPIO is not defined.
Note that after this the following boards which define
CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
conse
On Sat, Jul 3, 2021 at 4:35 AM Soeren Moch wrote:
>
> Hi Tim,
>
> On 01.07.21 19:34, Tim Harvey wrote:
> > If reset-gpio is defined by device-tree use that instead of a
> > board-specific function to toggle PCI reset.
> For me it looks like this: There is a common function that handles the
> reset
Some images may take a while to build, e.g. if they are large and use slow
compression. Support compiling sections in parallel to speed things up.
Signed-off-by: Simon Glass
---
tools/binman/binman.rst | 18 ++
tools/binman/cmdline.py | 4
tools/binman/control.
One of binman's attributes is that it is extremely fast, at least for a
Python program. Add some simple timing around operations that might take
a while, such as reading an image and compressing it. This should help
to maintain the performance as new features are added.
This is for debugging purpo
The constructor should not read the node information. Move it to the
ReadNode() method instead. This allows this etype to be subclassed.
Signed-off-by: Simon Glass
---
tools/binman/etype/files.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/binman/etype/files.py b/tools/binman/e
If the process outputs a lot of data on stdout this can be quite slow,
since the bytestring is regenerated each time. Use a bytearray instead.
Signed-off-by: Simon Glass
---
tools/patman/cros_subprocess.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/patman/cr
This is faster if data is being concatenated. Update the section and
collection etypes.
Signed-off-by: Simon Glass
---
tools/binman/etype/collection.py | 2 +-
tools/binman/etype/section.py| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/binman/etype/collection
When building an image with large files it makes sense to compress them in
parallel. This series adds support for this as well a few other
performance-related tweaks. It also includes support for timing of
the different types of operation (e.g. compression), for debugging
purposes.
Simon Glass (6
At present compression uses the same temporary file for all invocations.
With multithreading this causes the data to become corrupted. Use a
different filename each time.
Signed-off-by: Simon Glass
---
tools/patman/tools.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --
Introduce driver for I2C based MCP230xx GPIO chips, which are
quite common and already well supported by the Linux kernel.
Signed-off-by: Sebastian Reichel
---
drivers/gpio/Kconfig | 10 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/mcp230xx_gpio.c | 235
On 6/23/21 5:20 PM, Eugen Hristev wrote:
> gpio_request_by_name should be called with proper flags.
> The 0 value flag is invalid, and causes bad initialization of the gpio.
>
> Signed-off-by: Eugen Hristev
> ---
> drivers/w1/w1-gpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Sun, Jul 4, 2021 at 12:25 PM Marek Vasut wrote:
>
> On 7/4/21 5:35 PM, Fabio Estevam wrote:
> > Hi Marek,
>
> Hi,
>
> > On Sat, Jul 3, 2021 at 10:04 PM Marek Vasut wrote:
> >
> >>> Retrieving the USB base addresses from DT would be preferred, yes, but
> >>> the current code does not do that.
>
On Tue, Jul 06, 2021 at 04:57:32PM +0100, Andre Przywara wrote:
> On Tue, 6 Jul 2021 19:56:24 +0530
> Jagan Teki wrote:
>
> Hi Jagan,
>
> thanks for the response!
>
> > On Tue, Jul 6, 2021 at 4:53 AM Andre Przywara
> > wrote:
> > >
> > > The ums command (presenting a U-Boot block device as a
On 7/6/2021 6:43 PM, Tom Rini wrote:
I don't know if it's right either. But drawing on my comment just now
and above about complex boot scripts, I also don't know if "it's sh but
quirky and incomplete, WHY DOESN'T THIS WORK RIGHT" is better than "It's
TCL? I don't know that, let me hit stackove
Hi Tom,
The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
are available in the Git repository at:
g...@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 4b4
On 7/6/2021 6:33 PM, Tom Rini wrote:
Mature? And still without consequent error checking? And done,
i. e. this will never be fixed?
Intentional design by upstream, and then for the actual problem part
(error checking, test suite), Sean is saying he'll fix it, and has
started on it.
To clar
Hi Maxime,
Maxime Ripard wrote on Thu, 24 Jun 2021 14:05:40
+0200:
> Hi Miquel,
>
> On Wed, Feb 28, 2018 at 08:51:55PM +0100, Miquel Raynal wrote:
> > SPL support was first written to support only the earlier generations of
> > Allwinner SoCs, and was only really enabled on the A13 / GR8. Howev
On Tue, 6 Jul 2021 19:56:24 +0530
Jagan Teki wrote:
Hi Jagan,
thanks for the response!
> On Tue, Jul 6, 2021 at 4:53 AM Andre Przywara wrote:
> >
> > The ums command (presenting a U-Boot block device as a USB mass storage
> > device) is very useful for accessing eMMC devices via USB-OTG.
> >
>
On 7/6/21 10:45 AM, Tom Rini wrote:
On Tue, Jul 06, 2021 at 10:18:44AM -0500, Alex G. wrote:
On 5/31/21 12:43 PM, Alexandru Gagniuc wrote:
The purpose of this series is to allow booting an OP-TEE image from
SPL, by corectly configuring the TrustZone (TZC) memory regions.
Any chance we could
On Tue, Jul 06, 2021 at 08:57:23AM -0600, Simon Glass wrote:
> Hi Michael,
>
> On Tue, 6 Jul 2021 at 01:53, Michael Nazzareno Trimarchi
> wrote:
> >
> > On Tue, Jul 6, 2021 at 9:46 AM Wolfgang Denk wrote:
> > >
> > > Dear Sean,
> > >
> > > In message you wrote:
> > > >
> > > > >>> foo() {
On Tue, Jul 06, 2021 at 10:18:44AM -0500, Alex G. wrote:
> On 5/31/21 12:43 PM, Alexandru Gagniuc wrote:
> > The purpose of this series is to allow booting an OP-TEE image from
> > SPL, by corectly configuring the TrustZone (TZC) memory regions.
>
> Any chance we could have this hit the merge win
On Tue, Jul 06, 2021 at 09:44:20AM +0200, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <20210705191058.GB9516@bill-the-cat> you wrote:
> >
> > > > foo=bar set foo bar
> > > > echo $foo echo $foo
> > > >
> > > > if [ 1 -gt 2 ]; thenif {1
On Tue, Jul 06, 2021 at 09:52:56AM +0200, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <20210705185141.GA9516@bill-the-cat> you wrote:
> >
> > I think I want to try and address this. While with "hush" we have
> > something that's in heavy active development outside of U-Boot, with LIL
> > we
Hi Ilias,
On Mon, 5 Jul 2021 at 11:31, Ilias Apalodimas
wrote:
>
> Simon, Bin,
>
> As Heinrich points out some of the CONFIG_SYS_* values are not representing
> the devices properly. Maybe it's a better idea to only check the .dts?
> If the values are missing we can pop a runtime warning and keep
Hi Wolfgang,
On Tue, 6 Jul 2021 at 01:53, Wolfgang Denk wrote:
>
> Dear Tom,
>
> In message <20210705185141.GA9516@bill-the-cat> you wrote:
> >
> > I think I want to try and address this. While with "hush" we have
> > something that's in heavy active development outside of U-Boot, with LIL
> > w
Remove the mmc alias no more required as the sequence number
of mmc device is used for boot_instance.
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 1 -
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 2 --
2 files changed, 3 deletions(-)
diff --git a/arch/arm/dts/s
Use the device sequence number in boot_instance variable
and no more the SDMMC instance provided by ROM code/TF-A.
After this patch we don't need to define the mmc alias in
device tree, for example:
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
mmc2 = &sdmmc3;
to have a correct mapping between the ROM cod
On 5/31/21 12:43 PM, Alexandru Gagniuc wrote:
The purpose of this series is to allow booting an OP-TEE image from
SPL, by corectly configuring the TrustZone (TZC) memory regions.
Any chance we could have this hit the merge window?
Alex
devices can not boot properly during SPL stage by
using microSD card which model is SDSQUNC-032G-ZN6MA.
U-Boot SPL 2021.04 (Jul 02 2021 - 19:50:12 +)
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
change dts and config to sup
Host tool features, such as mkimage's ability to sign FIT images were
enabled or disabled based on the target configuration. However, this
misses the point of a target-agnostic host tool.
A target's ability to verify FIT signatures is independent of
mkimage's ability to create those signatures. In
Hi Michael,
On Tue, 6 Jul 2021 at 01:53, Michael Nazzareno Trimarchi
wrote:
>
> On Tue, Jul 6, 2021 at 9:46 AM Wolfgang Denk wrote:
> >
> > Dear Sean,
> >
> > In message you wrote:
> > >
> > > >>> foo() { proc foo {first second} {
> > > >>> echo $1 $2
Simplify the code a bit by using the common mmc_of_parse() function
instead of duplicating the device tree parsing code. We can still get
a default value for cfg->f_max by assigning it before calling
mmc_of_parse().
Another advantage of this refactoring is that we parse more properties
now, e.g. "
This patch series adds support for the eMMC on ST-Ericsson Ux500:
1. Some minor fixes+cleanup for the arm_pl180_mmci driver.
3. Add the necessary configuration for ST-Ericsson Ux500v2.
This was tested on the u8500 "stemmy" board that is already present
in U-Boot.
Stephan Gerhold (4):
mm
Simplify the code a bit by using dev_read_addr_ptr() instead of
dev_read_addr(). This avoids having to cast explicitly to void*.
Signed-off-by: Stephan Gerhold
---
drivers/mmc/arm_pl180_mmci.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/arm_pl180_mmci.
For the eMMC on ST-Ericsson Ux500v2 we need slightly different
configuration values. Use the existing switch statement to match
the peripheral ID of Ux500v2 (0x10480180) and override the necessary
values to make the eMMC work on devices with ST-Ericsson Ux500.
Cc: Linus Walleij
Signed-off-by: Ste
The arm,primecell compatible is used for lots of different types
of devices, e.g. I2C, SPI, coresight, ... We really should not bind
the MMC driver to all of them.
Looking through the device trees in U-Boot there seems to be always
a second compatible string for the pl180 device, either arm,pl180
On Tue, Jul 06, 2021 at 09:46:43AM +0200, Wolfgang Denk wrote:
> Dear Sean,
>
> In message you wrote:
> >
> > >>> foo() { proc foo {first second} {
> > >>> echo $1 $2 echo $first $second
> > >>> } }
> >
> > This is
Data transmission on the I2C4 bus is not required during the system boot
process,
so it is disabled
Signed-off-by: Xiaobo Tian
---
arch/arm/dts/rk3399-nanopi-r4s.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts
b/arch/arm/dts/rk3399-nanopi-r4s.dts
Remove the recommended MAC address from the network card.
NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which stores the MAC
address.
Signed-off-by: Xiaobo Tian
---
arch/arm/dts/rk3399-nanopi-r4s.dts | 15 ---
1 file changed, 15 deletions(-)
diff --git a/arch/arm/dts/r
The host-index-min property is invalid,
so it inherits from the sdmmc definition in dtsi.
Signed-off-by: Xiaobo Tian
---
arch/arm/dts/rk3399-nanopi-r4s.dts | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts
b/arch/arm/dts/rk3399-nanopi-r4s.dts
index 7470c2
Correct the LEDS label name and remove the board type prefix,
which is actually unnecessary here, removes the redefined system status LED pin.
Signed-off-by: Xiaobo Tian
---
arch/arm/dts/rk3399-nanopi-r4s.dts | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/r
Hi Heinrich,
On Mon, 5 Jul 2021 at 11:31, Heinrich Schuchardt wrote:
>
> On 7/4/21 10:15 PM, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Sun, 6 Jun 2021 at 15:35, Heinrich Schuchardt wrote:
> >>
> >> Am 6. Juni 2021 20:07:31 MESZ schrieb Sean Anderson :
> >>> On 6/6/21 1:57 PM, Heinrich Schuc
>From 29cf326e24b657180e4cf90ded2366d49f33e88e Mon Sep 17 00:00:00 2001
From: jason416
Date: Mon, 5 Jul 2021 23:22:29 +0800
Subject: [PATCH] rockchip: rk3328: fix booting error for nanopi-r2s
devices can not boot properly during SPL stage by
using microSD card which model is SDSQUNC-032G-ZN6MA.
On Tue, Jul 6, 2021 at 4:53 AM Andre Przywara wrote:
>
> The ums command (presenting a U-Boot block device as a USB mass storage
> device) is very useful for accessing eMMC devices via USB-OTG.
>
> At the moment we enable USB fastboot by default for Allwinner devices,
> so it makes sense to do the
On Tue, Jul 6, 2021 at 4:35 AM Andre Przywara wrote:
>
> The OrangePi Zero 2 board comes with 2MB of SPI flash, from which the
> BROM is supposed to be able to boot from.
>
> Enable the SPL code responsible for finding and loading U-Boot proper and
> friends, so that u-boot-sunxi-with-spl.bin can
On Tue, Jul 6, 2021 at 4:35 AM Andre Przywara wrote:
>
> The H616 SoC uses the same SPI IP as the H6, also shares the same clocks
> and reset bits.
> The only real difference is a slight change in the pin assignment: the
> H6 uses PC5, the H616 PC4 instead. This makes for a small change in
> our s
On Tue, Jul 6, 2021 at 4:35 AM Andre Przywara wrote:
>
> The more recent Allwinner SoCs BootROMs can actually load SPL images
> larger than 32KB. We use this on the H616 to fit the extra code needed
> for the PMIC into the image, and have provisions in board.c to respect
> that larger SPL size whe
Enable DM_PCI and DM_ETH on MIPS Malta.
Signed-off-by: Daniel Schwierzeck
---
arch/mips/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e54801673b..6b1f10d9a0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -14,8 +14,11 @@ c
As almost all peripherals are connected via PCI dependent on the
used core card, PCI setup is always required. Thus run pci_init()
including PCI scanning and probing and core card specific setups
in board_early_init_r().
Also prepare support for dynamically managing the status of the
different PCI
Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.
Signed-off-by: Daniel Schwierzeck
---
arch/mips/dts/mti,malta.dts | 28 +++
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
---
drivers/pci/pci_msc01.c | 70 -
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index 04838200a8
On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workar
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
---
drivers/pci/pci_gt64120.c | 72 ++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index 80f11f
This series converts the PCI host controller drivers used by MIPS
Malta and the board-specific PCI setup code to PCI driver model.
Because the AMD PCNET driver is already converted to ETH driver
model, simply enable CONFIG_DM_ETH as well.
A patch in PCI uclass core is currently required for MIPS
On Tue, Jul 6, 2021 at 9:06 AM Tom Rini wrote:
> On Tue, Jul 06, 2021 at 02:41:45AM -0400, Trevor Woerner wrote:
> > On Mon, Jul 5, 2021 at 11:13 AM Tom Rini wrote:
> >
> > > It is release day and here is the v2021.07 release.
> > >
> > > The merge window is once again open and I plan to tag -rc
On Tue, Jul 06, 2021 at 02:41:45AM -0400, Trevor Woerner wrote:
> On Mon, Jul 5, 2021 at 11:13 AM Tom Rini wrote:
>
> > It is release day and here is the v2021.07 release.
> >
> > The merge window is once again open and I plan to tag -rc1 on Monday,
> > July 26th, bi-weekly -rcs thereafter and fi
Hello Jagan,
Am Montag, den 05.07.2021, 11:01 +0530 schrieb Jagan Teki:
> On Fri, Jul 2, 2021 at 4:49 PM Teresa Remmet
> wrote:
> > Use now binman for image creation.
> >
> > Signed-off-by: Teresa Remmet
> > ---
> > .../imx8mp-phyboard-pollux-rdk-u-boot.dtsi| 105
> > ++
> >
On Wed, Jun 30, 2021 at 11:23:50PM +0800, Zong Li wrote:
> There are two revisions of unmatched board with different DDR timing,
> we'd like to support multi-dtb mechanism in SPL, then it selects the
> right DTB at runtime according to PCB revision in I2C EEPROM.
>
> Signed-off-by: Zong Li
> ---
On Wed, Jun 30, 2021 at 11:23:49PM +0800, Zong Li wrote:
> The difference between unmatched rev3 and rev1 is DDR timing, the rev3
> uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB.
>
> Signed-off-by: Zong Li
> ---
> arch/riscv/dts/Makefile |2 +-
> .../fu740-
On Wed, Jun 30, 2021 at 11:23:48PM +0800, Zong Li wrote:
> There are different DDR parameter settings for different board
> revisions. Add a new interface to get the PCB revision to determine
> which DT should be selected at runtime.
>
> Signed-off-by: Zong Li
> ---
> arch/riscv/include/asm/arch
On Wed, Jun 30, 2021 at 11:23:47PM +0800, Zong Li wrote:
> Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in
> i2c node.
>
> Signed-off-by: Zong Li
> ---
> arch/riscv/cpu/fu740/Kconfig | 1 +
> arch/riscv/dts/fu740-c000-u-boot.dtsi | 4
> 2 files changed, 5 inse
On Wed, Jun 30, 2021 at 11:23:46PM +0800, Zong Li wrote:
> Enable the Opencores I2C controller on FU740
>
> Signed-off-by: Zong Li
> ---
> arch/riscv/cpu/fu740/Kconfig | 2 ++
> board/sifive/unmatched/Kconfig | 1 +
> 2 files changed, 3 insertions(+)
>
Reviewed-by: Leo Yu-Chi Liang
On Wed, Jun 30, 2021 at 11:23:45PM +0800, Zong Li wrote:
> Add initial support for the PCB description EEPROM for SiFive HiFive
> Unmatched boards.
>
> This implementation is refactored based on Paul Walmsley's porting and
> adopt the suggestions from David Abdurachmanov.
>
> Signed-off-by: Paul
Hello Heiko,
Am Montag, den 05.07.2021, 06:58 +0200 schrieb Heiko Schocher:
> Hello Teresa,
>
> On 02.07.21 13:19, Teresa Remmet wrote:
> > With the first redesign the debug UART had changed from
> > UART2 to UART1.
> > As the first hardware revision is considered as alpha and
> > will not be sup
From: Chen Guanqiao
Fixed a defect of a null pointer being discovered by Coverity Scan:
CID 331544: Null pointer dereferences (REVERSE_INULL)
Null-checking "size" suggests that it may be null, but it has already been
dereferenced on all paths leading to the check.
Signed-off-by: Chen
This series includes a number of fixes and enhancements related to
enabling verified boot on Chromium OS:
- bloblist support for resizing and a few minor fixes
- iteration through block devices
- a few cros_ec improvements
- sandbox SDL2 fixes and support for launching the VPL executable
- minor t
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