Hi Maxime, Maxime Ripard <max...@cerno.tech> wrote on Thu, 24 Jun 2021 14:05:40 +0200:
> Hi Miquel, > > On Wed, Feb 28, 2018 at 08:51:55PM +0100, Miquel Raynal wrote: > > SPL support was first written to support only the earlier generations of > > Allwinner SoCs, and was only really enabled on the A13 / GR8. However, > > those old SoCs had a DMA engine that has been replaced since the A31 by > > another DMA controller that is no longer compatible. > > > > Since the code directly uses that DMA controller, it cannot operate > > properly on the later SoCs, while the NAND controller has not changed. > > > > There's two paths forward, the first one would have been to add support > > for that DMA controller too, the second to just remove the DMA usage > > entirely and rely on PIO. > > > > The later has been chosen because CPU overload at this stage is not an > > issue and it makes the driver more generic, and easier to understand. > > > > Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com> > > Acked-by: Boris Brezillon <boris.brezil...@bootlin.com> > > I'm a bit late to the party, but this bricks the CHIP Pro too. While > U-Boot proper seems to be flashed properly (re-reading it from the NAND > after flashing brings up the same CRC than the original image), the SPL > will only read 0s. > > The transfer does complete though, so maybe it's just the copy from the > SRAM to the main memory that doesn't work? > > The offset looks correct though, so I'm not sure. Strange... I really have no idea what's going on here and especially I don't have any suitable board with me these days to troubleshoot this. Sorry for not being helpful at all on this one :-) Thanks, Miquèl
