Hi xiaobo,
There is already a nonopi-r4s board, why we need a 1GB? This should
be already support.
Thanks,
- Kever
On 2021/6/8 上午9:28, xiaobo wrote:
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 1GiB(DDR3-1866) of RAM
Sig
On 08/06/2021 09:32, Lokesh Vutla wrote:
On 08/06/21 11:57 am, Tero Kristo wrote:
On 07/06/2021 14:22, Lokesh Vutla wrote:
On 03/06/21 12:02 pm, Tero Kristo wrote:
Hi,
As requested, this is just a rebase to the latest u-boot tip.
Boot tested on j721e to make sure nothing got broken.
Th
On 08/06/21 11:57 am, Tero Kristo wrote:
> On 07/06/2021 14:22, Lokesh Vutla wrote:
>>
>>
>> On 03/06/21 12:02 pm, Tero Kristo wrote:
>>> Hi,
>>>
>>> As requested, this is just a rebase to the latest u-boot tip.
>>>
>>> Boot tested on j721e to make sure nothing got broken.
>>
>> There are some b
On 07/06/2021 14:22, Lokesh Vutla wrote:
On 03/06/21 12:02 pm, Tero Kristo wrote:
Hi,
As requested, this is just a rebase to the latest u-boot tip.
Boot tested on j721e to make sure nothing got broken.
There are some build errors. Can you take a look?
https://source.denx.de/u-boot/custodia
I am calling qemu-x86_64_defconfig with
qemu-system-x86_64 -machine pc-i440fx-2.5 -m 1G -smp cores=2 \
-bios u-boot.rom -nographic -gdb tcp::1234 \
-drive file=../sandbox.img,if=none,format=raw,id=nvme1 \
-device nvme,drive=nvme1,serial="S3EWNX0J123456K" \
-netdev
Hi,
On 6/8/21 11:07 AM, Fabio Estevam wrote:
> Hi Haibo,
>
> On Mon, Jun 7, 2021 at 10:57 PM Bough Chen wrote:
>
>> Hi Fabio,
>>
>> Force clock on did help us fix some issue, like voltage switch for UHS card.
>> According to your commit log, seems this patch affect the booting time, do
>> you m
Hi Haibo,
On Mon, Jun 7, 2021 at 10:57 PM Bough Chen wrote:
> Hi Fabio,
>
> Force clock on did help us fix some issue, like voltage switch for UHS card.
> According to your commit log, seems this patch affect the booting time, do
> you mean
> the API readx_poll_timeout() cost a lot time? Can you
Sorry, the branch operation is wrong, I have revoked this patch.
Bin Meng 于2021年6月8日周二 上午9:39写道：
> On Tue, Jun 8, 2021 at 9:22 AM xiaobo wrote:
> >
> > From: Tom Rini
> >
> > Signed-off-by: Tom Rini
> > ---
> > Makefile | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> What i
Sorry, the branch operation is wrong, I have withdrawn this patch
alex tian 于2021年6月8日周二 上午9:59写道：
> Branch operation error error, I have withdrawn, sorry..
>
> Bin Meng 于2021年6月8日周二 上午9:39写道：
>
>> On Tue, Jun 8, 2021 at 9:22 AM xiaobo wrote:
>> >
>> > From: Tom Rini
>> >
>> > Signed-off-by:
Branch operation error error, I have withdrawn, sorry..
Bin Meng 于2021年6月8日周二 上午9:39写道：
> On Tue, Jun 8, 2021 at 9:22 AM xiaobo wrote:
> >
> > From: Tom Rini
> >
> > Signed-off-by: Tom Rini
> > ---
> > Makefile | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> What is this?
>
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2021年6月8日 4:40
> To: Peng Fan
> Cc: Bough Chen ; u-boot@lists.denx.de;
> thar...@gateworks.com; Fabio Estevam
> Subject: [PATCH v2] Revert "mmc: fsl_esdhc_imx: use
> VENDORSPEC_FRC_SDCLK_ON to control card cloc
On Tue, Jun 8, 2021 at 9:22 AM xiaobo wrote:
>
> From: Tom Rini
>
> Signed-off-by: Tom Rini
> ---
> Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
What is this?
Regards,
Bin
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 1GiB(DDR3-1866) of RAM
Signed-off-by: xiaobo
---
arch/arm/dts/Makefile | 1 +
.../arm/dts/rk3399-nanopi-r4s-1gb-u-boot.dtsi | 16 ++
arch/arm/dts/rk3399-nanop
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 1GiB(DDR3-1866) of RAM
Signed-off-by: xiaobo
---
arch/arm/dts/Makefile | 1 +
.../arm/dts/rk3399-nanopi-r4s-1gb-u-boot.dtsi | 16 ++
arch/arm/dts/rk3399-nanop
From: Tom Rini
Signed-off-by: Tom Rini
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index e048113ae2..a73481d18c 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAV
On Fri, May 07, 2021 at 02:50:28PM +0200, Patrick Delaunay wrote:
> Hi,
>
> It it the v4 serie of [1].
>
> This v4 serie is rebased on top of master branch with update after Simon
> Glass review and added tags.
>
> On STM32MP15x platform we can use OP-TEE, loaded in DDR in a region
> protected
On 6/7/21 4:38 PM, Yifeng Zhao wrote:
> This patch adds support for the RK3568 platform to this driver.
>
> Signed-off-by: Yifeng Zhao
> ---
>
> drivers/mmc/rockchip_sdhci.c | 103 +++
> 1 file changed, 103 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdh
Hi Yifeng,
On 6/7/21 4:38 PM, Yifeng Zhao wrote:
> Add clock, phy and other configuration, it is convenient to support
> new controller. Here a short summary of the changes:
> - support HS200 and HS400 config by dts
> - Remove OF_PLATDATA related code
> - Reorder header inclusion
> - Add data widt
This reverts commit 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2.
Since this commit a imx6qdl-pico board boots extremely slowly
in both SPL as well as U-Boot proper.
Fix this regression by reverting the offending commit for now.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Include the autho
I found this one left over in the queue ...
The following changes since commit e3b64beda5dd1a6b6bedfd1fe0e50be1ddea7044:
Prepare v2021.07-rc4 (2021-06-07 09:26:39 -0400)
are available in the Git repository at:
git://source.denx.de/u-boot-sh.git master
for you to fetch changes up to a2a148
On 07/06/21, Jorge Ramirez-Ortiz, Foundries wrote:
> hi Michal
>
> um, when we exchanged emails about enabling ECC support for MPSoC, I
> left with the understanding that there already was a DMA driver
> available in u-boot that I could use to initialize the memory.
>
> do you have something in t
In commit 1e4687aa47ed ("binman: Use target-specific tools when
cross-compiling"), a utility function was implemented to get preferred
compilation tools using environment variables like CC and CROSS_COMPILE.
Although it intended to provide custom default tools (same as those in
the global Makefile)
On 07/06/2021 18:48, Simon Glass wrote:
> From: Patrick Georgi
>
> The Chromium OS build system isn't particularly happy about using cc
> directly and fails the build when doing so.
>
> Update it to allow overriding this.
>
> Signed-off-by: Patrick Georgi
> Signed-off-by: Simon Glass
> ---
>
The default register configuration after powerup for PSSYSMON_ANALOG_BUS
register is incorrect. Hence, fix this in SPL by writing correct fixed
value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c")
in Xilinx:embeddedsw[
вс, 6 июн. 2021 г. в 19:47, Heinrich Schuchardt :
>
> On 6/6/21 6:21 PM, Heinrich Schuchardt wrote:
> > On 6/6/21 5:42 PM, Matwey V. Kornilov wrote:
> >> вс, 6 июн. 2021 г. в 18:20, Heinrich Schuchardt :
> >>>
> >>> On 6/6/21 4:37 PM, Matwey V. Kornilov wrote:
> Hi,
>
> I've found th
OrangePi PC2 board has DRAM with ODT, so enable it. ZQ value is also
slightly different in vendor images, so update it as well. H5 SoC is
also connected to voltage regulator. It's default value is pretty low,
so in order to avoid instability, enable driver for it and set it to
appropriate voltage.
вс, 6 июн. 2021 г. в 19:21, Heinrich Schuchardt :
>
> On 6/6/21 5:42 PM, Matwey V. Kornilov wrote:
> > вс, 6 июн. 2021 г. в 18:20, Heinrich Schuchardt :
> >>
> >> On 6/6/21 4:37 PM, Matwey V. Kornilov wrote:
> >>> Hi,
> >>>
> >>> I've found that
> >>>
> >>> f3866909e350 ("distro_bootcmd: call EFI b
On 6/7/21 9:54 AM, Kunihiko Hayashi wrote:
Hi,
[...]
I would expect that after relocation, if all you have is env_nowhere
driver, the env_nowhere_init() is called again from the first for()
loop
of env_init() [1], which would set gd->env_valid to ENV_INVALID [1],
and
that for() loop would ex
Hi all,
There seems to be a bug in combination with RPI4 and 2 HDD-s are connected over
same USB port. When HDD-s are present, then u-boot is not able to boot up OS
from SD card.
Created a FreeBSD bug report about this issue. However it seems not to be
FreeBSD problem, but U-Boot bug instead.
hi Michal
um, when we exchanged emails about enabling ECC support for MPSoC, I
left with the understanding that there already was a DMA driver
available in u-boot that I could use to initialize the memory.
do you have something in the works or will I have to write such a
driver? compatible would
From: Patrick Georgi
The Chromium OS build system isn't particularly happy about using cc
directly and fails the build when doing so.
Update it to allow overriding this.
Signed-off-by: Patrick Georgi
Signed-off-by: Simon Glass
---
tools/dtoc/fdt_util.py | 1 +
1 file changed, 1 insertion(+)
On Sat, Jun 05, 2021 at 03:37:01PM +0800, Jon Lin wrote:
>
> On 6/4/21 10:40 PM, Chris Morgan wrote:
> > On Fri, Jun 04, 2021 at 09:42:18PM +0800, 林鼎强 wrote:
> > > Hi Chris:
> > >
> > > It's my honor to read about spi-rockchip-sfc driver from you, and your
> > > code has made a big difference to
On 6/7/21 11:14 AM, Maxime Ripard wrote:
> On Mon, May 24, 2021 at 11:43:43AM -0400, Sean Anderson wrote:
>>
>>
>> On 5/24/21 11:28 AM, Maxime Ripard wrote:
>>> On Mon, May 24, 2021 at 10:37:31AM -0400, Sean Anderson wrote:
On 5/23/21 8:36 PM, Andre Przywara wrote:
> At the
On Mon, May 24, 2021 at 11:43:43AM -0400, Sean Anderson wrote:
>
>
> On 5/24/21 11:28 AM, Maxime Ripard wrote:
> > On Mon, May 24, 2021 at 10:37:31AM -0400, Sean Anderson wrote:
> >>
> >>
> >> On 5/23/21 8:36 PM, Andre Przywara wrote:
> >>> At the moment the fastboot code relies on the Kconfig va
Configure blinking on ethernet PHY LEDs on the MOX A board when entering
rescue mode via reset button.
Signed-off-by: Marek Behún
---
board/CZ.NIC/turris_mox/turris_mox.c | 35
1 file changed, 35 insertions(+)
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c
b/boa
Add nodes for SPI NOR partitions to the device tree of Turris MOX, as
are in Linux' device tree.
Signed-off-by: Marek Behún
---
arch/arm/dts/armada-3720-turris-mox.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
b/arch/a
Enable configuration options to support Turris network boot. This
includes FIT support and some crypto commands.
Signed-off-by: Marek Behún
---
configs/turris_mox_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
ind
Add default fdtfile environment variable with value
marvell/armada-3720-turris-mox.dtb.
This can be useful for some boot scenarios.
Signed-off-by: Marek Behún
---
include/configs/turris_mox.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/turris_mox.h b/include/configs/turr
Add necessary config options and board code to support board factory
reset / rescue mode on Turris MOX.
In order to also support invoking rescue mode from U-Boot console,
without having to press the factory reset button, put the rescue command
into `bootcmd_rescue` default environment variable. Wh
Add nodes for indicator LED and reset button so that board code can
implement board factory reset mechanism.
Signed-off-by: Marek Behún
---
arch/arm/dts/armada-3720-turris-mox.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/dts/armada-3720-turris-mox.dt
Hello Stefan,
Here are some changes for Turris MOX (v2):
- dts changes
- more config options enabled
- rescue mode support added
If it is possible, since this touches only our device, we would like
this to be also merged for v2021.07 (once reviewed by you and Pali).
Changes since v1:
- use const
Hey all,
It's release day, and here's v2021.07-rc4. I'm getting this out early
in the day as this is also when I'm opening the -next branch. I'm going
to go over my queue and start putting things in there myself and hope
for PRs from various maintainers soon.
We did bring in the LTO series now,
On 07.06.21 14:36, Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM
> module with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
>
> The matching evaluation boards (Board-Line) have 2 Ethernets, USB 2
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers.
Add support for the same.
Note that we still need to send chan/flow cfg message to TIFS via TISCI
client driver in order to open up firewalls around chan/flow but
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup Ring Cfg registers. Add support for
the same.
Note that we still need to send RING_CFG message to TIFS via TISCI
client driver in order to open up firewalls around Rings.
U-Boot specific code is
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Note that these registers are present within respective IPs but are
not populated in Linux DT nodes (as they are configured via TISCI APIs)
and hence are added to -u-boot.dtsi for no
Add DM firmware node which will provide DM services during R5 SPL stage.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 17 +
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++
2 files changed, 35 insertions(+)
diff -
On J721e and J7200, MCU R5 core (boot master) itself would run Device
Manager (DM) Firmware and interact with TI Foundational Security (TIFS)
firmware to enable DMA and such other Resource Management (RM) services.
So, during R5 SPL stage there is no such RM service available and ti_sci
driver will
R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads.
Mark these as valid threads in the driver.
Signed-off-by: Vignesh Raghavendra
---
drivers/mailbox/k3-sec-proxy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mail
In case of R5 SPL, GET_RANGE API service is not available (as DM
services are not yet up), therefore service such calls locally using
per SoC static data.
Signed-off-by: Vignesh Raghavendra
---
drivers/firmware/ti_sci.c | 36 +++
drivers/firmware/ti_sci_static_data.h | 92 +++
This series add DMA support for R5 SPL on J721e/J7200 SoCs post HSM
Rearch.
Depends on Tero's base HSM rearch support series.
v2:
Use IS_ENABLED() consistentially instead of #ifdef
Reword commit msg for 5/7 as suggested by Lokesh
Rebase on Tero's latest HSM base series.
Vignesh Raghavendra (7):
Macronix NAND Flash devices are available in different configurations
and densities.
MX"35" means SPI NAND
MX35"UF" , UF meands 1.8V
MX35LF"2G" , 2G means 2Gbits
MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4)
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial
NAND flash device
Change in v2:
- remove spinand Flash IDs which are sw-ecc requirement
cause sw-ecc function is not supported in u-boot
v1:
- Add spinand Flash IDs in drivers/mtd/nand/spi/macronix.c
Jaime Liao (1):
mtd: spinand: macronix: Add support for serial NAND flash
drivers/mtd/nand/spi/macronix.c | 4
Hi Miquel
> "Miquel Raynal"
> 2021/06/07 下午 02:13
>
> 收件人
>
> zhengxu...@mxic.com.tw,
>
> 副本抄送
>
> ja...@amarulasolutions.com, "Jaime Liao" , u-
> b...@lists.denx.de, vigne...@ti.com, ycl...@mxic.com.tw
>
> 主旨
>
> Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND flash
>
>
From: Frieder Schrempf
The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM
module with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
The matching evaluation boards (Board-Line) have 2 Ethernets, USB 2.0,
HDMI/LVDS,
SD card, CAN, RS485 and much more.
Sig
From: Frieder Schrempf
This adds support for i.MX6UL/ULL-based evaluation kits with SoMs by
Kontron Electronics GmbH.
Currently there are the following SoM flavors (SoM-Line):
* N6310: SOM with i.MX6UL-2, 256MB RAM, 256MB SPI NAND
* N6311: SOM with i.MX6UL-2, 512MB RAM, 512MB SPI NAND
* N6
From: Frieder Schrempf
Some IPs have their accessible address space restricted by the
interconnect. Let's make sure U-Boot only ever uses the space below
the 4G address boundary (which is 3GiB big), even when the effective
available memory is bigger.
We implement board_get_usable_ram_top() for a
From: Frieder Schrempf
Add the clocks for the ECSPI controllers. This is ported from
Linux v5.13-rc4.
Signed-off-by: Frieder Schrempf
---
drivers/clk/imx/clk-imx8mm.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/driv
From: Frieder Schrempf
The driver depends on DM_SPI and if it's not available (e. g. in SPL),
then we should not try to build it as this will fail.
Signed-off-by: Frieder Schrempf
---
drivers/spi/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Makefile
From: Frieder Schrempf
The MX25V8035F is a 8Mb SPI NOR flash and the MX25R1635F is very
similar, but has twice the size (16Mb) and supports a wider supply
voltage range.
They were tested on the Kontron Electronics i.MX6UL and i.MX8MM SoMs.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi/s
From: Frieder Schrempf
These SoMs and boards are developed and sold by Kontron Electronics
GmbH. All basic peripherals for booting are supported.
Patches 1 to 4 are for preparation. Patch 5 adds support for the
i.MX6UL/ULL boards and patch 6 for the i.MX8MM boards.
---
Resending with ML subscrip
From: Frieder Schrempf
The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM
module with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
The matching evaluation boards (Board-Line) have 2 Ethernets, USB 2.0,
HDMI/LVDS,
SD card, CAN, RS485 and much more.
Sig
From: Frieder Schrempf
This adds support for i.MX6UL/ULL-based evaluation kits with SoMs by
Kontron Electronics GmbH.
Currently there are the following SoM flavors (SoM-Line):
* N6310: SOM with i.MX6UL-2, 256MB RAM, 256MB SPI NAND
* N6311: SOM with i.MX6UL-2, 512MB RAM, 512MB SPI NAND
* N6
From: Frieder Schrempf
Some IPs have their accessible address space restricted by the
interconnect. Let's make sure U-Boot only ever uses the space below
the 4G address boundary (which is 3GiB big), even when the effective
available memory is bigger.
We implement board_get_usable_ram_top() for a
From: Frieder Schrempf
The MX25V8035F is a 8Mb SPI NOR flash and the MX25R1635F is very
similar, but has twice the size (16Mb) and supports a wider supply
voltage range.
They were tested on the Kontron Electronics i.MX6UL and i.MX8MM SoMs.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi/s
From: Frieder Schrempf
The driver depends on DM_SPI and if it's not available (e. g. in SPL),
then we should not try to build it as this will fail.
Signed-off-by: Frieder Schrempf
---
drivers/spi/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Makefile
From: Frieder Schrempf
Add the clocks for the ECSPI controllers. This is ported from
Linux v5.13-rc4.
Signed-off-by: Frieder Schrempf
---
drivers/clk/imx/clk-imx8mm.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/driv
From: Frieder Schrempf
These SoMs and boards are developed and sold by Kontron Electronics
GmbH. All basic peripherals for booting are supported.
Patches 1 to 4 are for preparation. Patch 5 adds support for the
i.MX6UL/ULL boards and patch 6 for the i.MX8MM boards.
Frieder Schrempf (6):
mtd:
This driver supports Rockchip NFC (NAND Flash Controller) found on
RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been
tested using 8-bit NAND interface on the ARM based RK3308 platform.
Support Rockchip SoCs and NFC versions:
- PX30 and RK3326(NFCv900).
ECC: 16/40/60/70 bit
Add clock, phy and other configuration, it is convenient to support
new controller. Here a short summary of the changes:
- support HS200 and HS400 config by dts
- Remove OF_PLATDATA related code
- Reorder header inclusion
- Add data width config for 1, 4, 8 bits
- Add phy ops
- add ops set_ios_post
This patch adds support for the RK3568 platform to this driver.
Signed-off-by: Yifeng Zhao
---
drivers/mmc/rockchip_sdhci.c | 103 +++
1 file changed, 103 insertions(+)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 05ed998eca..be
RK3399 and RK3568 are use different sdhci controllers.
The drivers need to be updated to support these two platforms
and it's easy to support new platforms.
Yifeng Zhao (2):
mmc: rockchip_sdhci: add phy and clock config for rk3399
mmc: rockchip_sdhci: Add support for RK3568
drivers/mmc/rockc
Signed-off-by: Christian Melki
---
disk/part_dos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 60addc6e00..9e29aa6583 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -424,7 +424,7 @@ int write_mbr_partitions(struct blk_desc *de
A newer toolchain will emit udivmoddi4 for certain divide + modulo
operations instead of a separate divide and modulo operation.
AFAIU, this would be sufficient.
Signed-off-by: Christian Melki
---
arch/x86/lib/div64.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/lib/div64.c
On 6/7/21 2:05 PM, Frieder Schrempf wrote:
From: Frieder Schrempf
Some IPs have their accessible address space restricted by the
interconnect. Let's make sure U-Boot only ever uses the space below
the 4G address boundary (which is 3GiB big), even when the effective
available memory is bigger.
This patch add support for using NXP's pca8574 I2C IO expander, which
has only 8 IO lines.
After this change the .data member's information from struct udevice_id
are used to either sent one or two bytes.
Moreover, the '_le16' suffix from pcf8575_i2c_{write|read}_le16()
functions have been remove
Those members are not used anymore as ones from gpio_dev_priv
structure (when DM_GPIO support is enabled) are used instead.
Signed-off-by: Lukasz Majewski
---
drivers/gpio/pcf8575_gpio.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpi
On 5/21/21 11:52 AM, Tudor Ambarus wrote:
> This reverts commit 786f888b743e9b83c9095cb9b5548ebe2e29afc5.
>
> Looks like the datasheet at
> https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D3-Series-Data-sheet-DS60001609b.pdf
> is wrong, and the testing was poorly done, because the PMECC did
On 07.06.21 13:40, Tom Rini wrote:
> On Mon, Jun 07, 2021 at 03:33:52PM +0530, Lokesh Vutla wrote:
>> +Tom,
>>
>> Hi Tom,
>>
>> On 02/06/21 3:07 pm, Jan Kiszka wrote:
>>> From: Jan Kiszka
>>>
>>> To avoid the need of extra boot scripting on AM65x for loading a
>>> watchdog firmware, add the requir
On Mon, Jun 07, 2021 at 03:33:52PM +0530, Lokesh Vutla wrote:
> +Tom,
>
> Hi Tom,
>
> On 02/06/21 3:07 pm, Jan Kiszka wrote:
> > From: Jan Kiszka
> >
> > To avoid the need of extra boot scripting on AM65x for loading a
> > watchdog firmware, add the required rproc init and loading logic for the
On 28/05/21 3:00 pm, gireesh.hirem...@in.bosch.com wrote:
> From: Gireesh Hiremath
>
> address the v2 review comments
>
>> Hi Gireesh,
>>
>> On 22/04/21 7:01 pm, gireesh.hirem...@in.bosch.com wrote:
>>> From: Gireesh Hiremath
>>>
>>> add support for updated TI clock driver, backlight, splash
On Mon, Jun 07, 2021 at 11:32:56AM +0800, Kever Yang wrote:
> Hi Tom,
>
> Please pull the rockchip updates/fixes:
> - Maintainer mail address update
>
> DENX ci:
> https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/7676
>
> Thanks,
> - Kever
>
> The following changes since co
On 03/06/21 12:02 pm, Tero Kristo wrote:
> Hi,
>
> As requested, this is just a rebase to the latest u-boot tip.
>
> Boot tested on j721e to make sure nothing got broken.
There are some build errors. Can you take a look?
https://source.denx.de/u-boot/custodians/u-boot-ti/-/jobs/275511
Thanks
On Sun, Jun 06, 2021 at 10:42:08AM -0600, Simon Glass wrote:
> Hi Tom,
>
> https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/7711
>
>
> The following changes since commit c003d2cd6b415319c3e40db42b48c2815acda3d3:
>
> Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
On Sat, Jun 05, 2021 at 03:00:56PM +0200, Anatolij Gustschin wrote:
> Hi Tom,
>
> please pull new video patches for v2021.07-rc3.
>
> gitlab CI:
> https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/7704
>
> Thanks!
>
> The following changes since commit c003d2cd6b415319c3e40db4
Xilinx ZynqMP supports also addresses above 4GB (32bit) that's why also
generate u-boot.its with 64bit load/entry addresses to also support
different configurations.
Signed-off-by: Michal Simek
---
arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 22 +++---
1 file changed, 15 insertion
Hi Tim,
On 27.05.21 17:41, Tim Harvey wrote:
Greetings,
I support various iMX8M PCB's via board/gateworks/venice that are SOM
based and we are starting to add SOM's that have different IMX8M variant
SoC's on them which for various reasons are not binary compatible. I'm
very interested in com
On 07.06.21 12:03, Lokesh Vutla wrote:
> +Tom,
>
> Hi Tom,
>
> On 02/06/21 3:07 pm, Jan Kiszka wrote:
>> From: Jan Kiszka
>>
>> To avoid the need of extra boot scripting on AM65x for loading a
>> watchdog firmware, add the required rproc init and loading logic for the
>> first R5F core to the wa
Linux kernel is not using these properties that's why they can be removed.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index d7e551630d6f..7de7166bd7fb 100644
--- a/arch/a
psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 14 +++---
arch/arm/dts/zynqmp-zcu104-revA.dts | 14 +++---
arch/arm/dts/zyn
Clock setting is not static anymore that's why it depends on firmware setup
that's why remove this comment.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu106-revA.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts
b/arch/arm/dts/zynqmp-zcu106-re
Convert all boards to use nvmem alias instead of xlnx,eeprom. The change is
done based on discussion in the link below.
Link:
https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_...@mail.gmail.com
Signed-off-by: Michal Simek
---
Information about board is shown as:
Model
Networking subsystem is not using aliases that's why remove them for CAN
devices. There is also no any other Xilinx ZynqMP DT file with them.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 --
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 --
2 files changed, 4 dele
There are no drivers for these devices that's why remove that nodes
completely. This change is done based on Linux kernel.
Signed-off-by: Michal Simek
Link:
https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.w...@windriver.com
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 10 +-
a
From: Srinivas Neeli
As per the design specification
"The 16-bit Seconds Calibration Value represents the number of
Oscillator Ticks that are required to measure the largest time
period that is less than or equal to 1 second.
For an oscillator that is 32.768 KHz, this value will be 0x7FFF."
S
Hi,
this is the next series which is trying to clean and sync DTS files.
At the end we want to have all these files be in sync with the Linux kernel
based on DT binding available in the Linux kernel.
Thanks,
Michal
Michal Simek (6):
xilinx: Convert xlnx,eeprom property to nvmem alias
arm64:
+Tom,
Hi Tom,
On 02/06/21 3:07 pm, Jan Kiszka wrote:
> From: Jan Kiszka
>
> To avoid the need of extra boot scripting on AM65x for loading a
> watchdog firmware, add the required rproc init and loading logic for the
> first R5F core to the watchdog start handler. In case the R5F cluster is
> in
On Monday 07 June 2021 14:57:55 Lokesh Vutla wrote:
> On 10/03/21 1:49 am, Pali Rohár wrote:
> > Also convert CONFIG_HW_WATCHDOG to CONFIG_WATCHDOG.
> >
> > Signed-off-by: Pali Rohár
> > ---
> > This patch increase u-boot.bin binary size above maximal limit. So this
> > patch cannot be applied ye
On 10/03/21 1:49 am, Pali Rohár wrote:
> Also convert CONFIG_HW_WATCHDOG to CONFIG_WATCHDOG.
>
> Signed-off-by: Pali Rohár
> ---
> This patch increase u-boot.bin binary size above maximal limit. So this
> patch cannot be applied yet. But it can be applied on top of the LTO
> patches. So please
On 12/05/21 14:39, Mauro Salvini wrote:
Raspberry firmware prepares the FDT blob in memory at an address
that depends on both the memory size and the blob size [1].
After commit ade243a211d6 ("rpi: passthrough of the firmware provided FDT
blob") this FDT is passed to kernel through fdt_addr envir
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