From: Frieder Schrempf <frieder.schre...@kontron.de>
Some IPs have their accessible address space restricted by the
interconnect. Let's make sure U-Boot only ever uses the space below
the 4G address boundary (which is 3GiB big), even when the effective
available memory is bigger.
We implement board_get_usable_ram_top() for all i.MX8M SoCs, as the
whole family is affected by this.
Signed-off-by: Frieder Schrempf <frieder.schre...@kontron.de>
---
arch/arm/mach-imx/imx8m/soc.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 0c44022a6d..f5983320c7 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -296,6 +296,20 @@ phys_size_t get_effective_memsize(void)
#endif
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ /*
+ * Some IPs have their accessible address space restricted by
+ * the interconnect. Let's make sure U-Boot only ever uses the
+ * space below the 4G address boundary (which is 3GiB big),
+ * even when the effective available memory is bigger.
+ */
+ if (PHYS_SDRAM + gd->ram_size > 0x80000000)
+ return 0x80000000;
+
+ return PHYS_SDRAM + gd->ram_size;
+}
+
static u32 get_cpu_variant_type(u32 type)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
--
2.25.1
