On Wed, Oct 09, 2019 at 02:30:44PM +0900, AKASHI Takahiro wrote:
> This function, and hence rsa_verify(), will perform RSA verification
> with two essential parameters for a RSA public key in contract of
> rsa_verify_with_keynode(), which requires additional three parameters
> stored in FIT image.
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> Change the algorithm to first find the flash device then read the
> properties using the livetree API. With this change the device is not
> probed so this needs to be done in mrccache_save().
>
> Signed-off-by: Simon Glass
> ---
>
On Fri, Oct 4, 2019 at 7:04 PM Marek Vasut wrote:
>
> On 10/4/19 10:59 AM, Ley Foon Tan wrote:
> > On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
> >>
> >> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
> >> accordingly, no functional change. The S10 enables the WDT only i
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> This should take account of the end of the new cache record since a record
> cannot extend beyond the end of the flash region. This problem was not
> seen before due to the alignment of the relatively small amount of MRC
> data.
>
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Signed-off-by: Ley Foon Tan
---
v3:
- Remove "No functional change" in commit description.
v2:
- Revert to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
arch/arm/mach-socf
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Signed-off-by: Ley Foon Tan
---
v3:
- Remove "No functional change" in commit description.
v2:
- Revert to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
arch/arm/mach-socfp
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Signed-off-by: Ley Foon Tan
---
v3:
- Remove "No functional change" in commit description.
v2:
- Get base address from DT
- Revert to use writel(), readl(), setbits_le32() and clrbits_le32().
- Add prefix to defines
This is 3rd version of patchset to convert reset, system and clock manager
drivers to use #define instead of struct.
Only patch 1 had minor fix for missing '0' in clkmgr DT node, other pataches
are
unchanged.
Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
Changes in v3:
- Patch 1: Minor
Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v3:
- Fix missing '0' in clkmgr@ffd1 node.
---
arch/arm/dts/socfpga-common-u-boot.dtsi | 8
arc
On 10/10/19 2:50 AM, AKASHI Takahiro wrote:
On Wed, Oct 09, 2019 at 07:41:40PM +0200, Heinrich Schuchardt wrote:
On 10/9/19 9:19 AM, AKASHI Takahiro wrote:
There is no practical reason to set a maxmum length of text either for
file path or whole device path in device path-to-text conversion.
S
On 10.10.19 07:52, Vignesh Raghavendra wrote:
AM654/J721e has HyperBus Memory Controller that supports HyperFlash and
HyperRAM devices. It provides a memory mapped interface to interact with
these devices. Add a driver to support the same.
Driver calibrates the controller, setups up for MMIO acce
On 10.10.19 07:52, Vignesh Raghavendra wrote:
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.
Signed-off-by: Vignesh Raghavendra
---
v2:
Make macro check consistent as pointed out by Stefan
Reviewed-by: Stefan Roese
T
Define CONFIG_SYS_MAX_FLASH_BANKS_DETECT so that number of flash banks
are automatically detected by CFI flash driver
Signed-off-by: Vignesh Raghavendra
---
include/configs/j721e_evm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the
same.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-j721e-som-p0.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi
b/arch/arm/dts/k3-j721e-s
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not
possible to use OSPI0 and HBMC simultaneously as they are muxed within
the Flash Subsystem hence disable HBMC by default as keep OSPI enabled.
Bootloader will fixup DT when it detects HyperFlash instead of OSPI.
Signed-off-by
Enable HBMC and HyperFlash in A72 SPL and A72 U-Boot
Signed-off-by: Vignesh Raghavendra
---
configs/j721e_evm_a72_defconfig | 12
1 file changed, 12 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 5cb933d87886..7ddf85fea743 100644
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.
Signed-off-by: Vignesh Raghavendra
---
v2:
Make macro check consistent as pointed out by Stefan
drivers/mtd/cfi_flash.c | 6 --
1 file changed, 4 insertions(+), 2 deleti
AM654/J721e has HyperBus Memory Controller that supports HyperFlash and
HyperRAM devices. It provides a memory mapped interface to interact with
these devices. Add a driver to support the same.
Driver calibrates the controller, setups up for MMIO access and probes
HyperFlash child node.
Signed-off
This series adds support for HyperBus Memory Controller of TI's J721e
and AM654 SoCs.
Vignesh Raghavendra (6):
mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined
mtd: Add TI HyperBus Memory Controller driver
arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
arm: dts:
Marek Vasut schrieb am Mi., 9. Okt. 2019, 23:01:
> On 10/9/19 8:06 PM, Simon Goldschmidt wrote:
> [...]
> >>> Based on my understand through this register
> >>> fpga_mgr_fpgamgrdata
> >>> address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
> >>> of
> >>> FIFO
>
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> Move the code to determine the size of a cache record into a function so
> we can use it elsewhere in this file.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/lib/mrccache.c | 15 ---
> 1 file changed, 8 insertions(+), 7 del
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> At present the records are 4KB in size. This is unnecessarily large when
> the SPI-flash erase size is 256 bytes. Reduce it so it will be more
But this will break for SPI-flash erase size that is not 256 bytes?
> efficient with A
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> The Primary-to-Sideband bus (P2SB) is used to access various peripherals
> through memory-mapped I/O in a large chunk of PCI space. The space is
> segmented into different channels and peripherals are accessed by
> device-specific
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> The write functions do actually change the contents of memory so it is not
> correct to use 'const'. Remove it.
>
> Signed-off-by: Simon Glass
> ---
>
> common/iotrace.c | 6 +++---
> include/iotrace.h | 13 ++---
> 2 files change
Hi Simon,
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> Intel x86 SoCs have a power manager/controller which handles several
> power-related aspects of the platform. Add a uclass for this, with a few
> useful operations.
>
I don't like to create another x86 specific uclass for this pow
Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass wrote:
>
> This models some sort of interrupt thingy but there are so many
> abreviations that I cannot find out what it stands for. It is something
> to do with interrupts.
>
After I read the ApolloLake datasheet, the ITSS contains the foll
Hi Peter,
On 2019/10/9 下午8:01, Peter Robinson wrote:
On Wed, Oct 9, 2019 at 11:08 AM Kever Yang wrote:
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now
On Wed, Oct 09, 2019 at 07:56:04PM +0200, Heinrich Schuchardt wrote:
> On 10/9/19 7:30 AM, AKASHI Takahiro wrote:
> >This function, and hence rsa_verify(), will perform RSA verification
> >with two essential parameters for a RSA public key in contract of
> >rsa_verify_with_keynode(), which requires
On Thu, Oct 10, 2019 at 2:42 AM Simon Goldschmidt
wrote:
>
> Am 02.10.2019 um 11:23 schrieb Simon Goldschmidt:
> > On Wed, Oct 2, 2019 at 10:13 AM Ley Foon Tan wrote:
> >>
> >> On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
> >> wrote:
> >>>
> >>>
> >>>
> >>> Ley Foon Tan schrieb am Mi., 18
On Wed, Oct 09, 2019 at 07:41:40PM +0200, Heinrich Schuchardt wrote:
> On 10/9/19 9:19 AM, AKASHI Takahiro wrote:
> >There is no practical reason to set a maxmum length of text either for
> >file path or whole device path in device path-to-text conversion.
> >
> >Signed-off-by: AKASHI Takahiro
> >
On 10/9/19 8:06 PM, Simon Goldschmidt wrote:
[...]
>>> Based on my understand through this register
>>> fpga_mgr_fpgamgrdata
>>> address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
>>> of
>>> FIFO
>>> buffer is mapping to above range addresses.
>> 0xFFCFE7FF-0
On 10/9/19 8:20 PM, Simon Goldschmidt wrote:
> Marek,
Hello Simon,
> Am 27.06.2019 um 00:19 schrieb Marek Vasut:
>> The company Samtec was merged into Softing, migrate the board over to
>> the new name and update copyright headers.
>
> What happened to this series?
I applied it now.
___
On Wed, Oct 09, 2019 at 11:04:13AM -0400, Tom Rini wrote:
> Build the keystone 3 platforms with the keystone 2 platforms, in order
> to get back more room in the "catch-all" build jobs.
>
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signa
> The following changes since commit 61ba1244b548463dbfb3c5285b6b22e7c772c5bd:
>
> Prepare v2019.10 (2019-10-07 17:14:02 -0400)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
> tags/
On Wed, Oct 09, 2019 at 11:04:12AM -0400, Tom Rini wrote:
> As both "catch-all" ARM jobs are nearing their time limit, move all of
> the bcm SoC boards into a single job.
>
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
__
Am 02.10.2019 um 11:23 schrieb Simon Goldschmidt:
On Wed, Oct 2, 2019 at 10:13 AM Ley Foon Tan wrote:
On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
wrote:
Ley Foon Tan schrieb am Mi., 18. Sep. 2019, 04:32:
On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen wrote:
On 9/10/19 3:37 AM,
Hi Adam
On Tuesday, October 08, 2019 15:31 -03, Adam Ford wrote:
> The pfuze100 is the PMIC connected to the I2C bus. Currently,
> the I2C driver is disabled which prevents the PMIC from operating.
>
> This patch enables the I2C which also enables the PMIC in U-Boot.
> This also keeps the
Am 24.05.2019 um 14:16 schrieb Chee, Tien Fong:
On Fri, 2019-05-24 at 14:00 +0200, Simon Goldschmidt wrote:
On Fri, May 24, 2019 at 1:57 PM Chee, Tien Fong
wrote:
On Fri, 2019-05-24 at 13:53 +0200, Simon Goldschmidt wrote:
On Fri, May 24, 2019 at 1:44 PM Marek Vasut
wrote:
On 5/24/19
Marek,
Am 27.06.2019 um 00:19 schrieb Marek Vasut:
The company Samtec was merged into Softing, migrate the board over to
the new name and update copyright headers.
What happened to this series?
Regards,
Simon
Signed-off-by: Marek Vasut
Cc: Silvio Fricke
Cc: Simon Goldschmidt
---
arch/
Am 02.08.2019 um 16:41 schrieb Simon Glass:
Hi SImon,
On Thu, 1 Aug 2019 at 23:53, Simon Goldschmidt
wrote:
On Fri, Aug 2, 2019 at 12:45 AM Simon Glass wrote:
Hi Simon,
On Mon, 29 Jul 2019 at 04:47, Simon Goldschmidt
wrote:
Simon,
On Wed, Jul 10, 2019 at 8:50 PM Simon Goldschmidt
wro
On Wed, Oct 9, 2019 at 2:54 PM Adam Ford wrote:
>
> With the OCRAM expanded to 256KB and the SPL_PINCTRL enabled with
> -u-boot.dtsi entries to include the pinmuxing in SPL, the manual
> code setting up the pinmux can go away.
>
> This patch removes the legacy pinmuxing code from the board file.
>
Marek,
Am 13.05.2019 um 15:12 schrieb Marek Vasut:
On 5/13/19 2:58 PM, Chee, Tien Fong wrote:
On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
On Wed, Oct 9, 2019 at 2:54 PM Adam Ford wrote:
>
> With the 256KB of OCRAM available to SPL now, there should be
> enough room to enable the pinmuxing in SPL from the device tree.
>
> This patch enables SPL_PINCTRL et al and adds the serial and
> usdhc pin mux references to the -u-boot.dtsi file
On Wed, Oct 9, 2019 at 2:54 PM Adam Ford wrote:
>
> Since this board config only supports, the i.MX6D/i.MX6Q configurations,
> 256K of on-chip RAM is available which increases the space available
> to SPL to help further reduce board code and further enable device tree
> functions.
>
> This patch
On 10/9/19 7:30 AM, AKASHI Takahiro wrote:
This function, and hence rsa_verify(), will perform RSA verification
with two essential parameters for a RSA public key in contract of
rsa_verify_with_keynode(), which requires additional three parameters
stored in FIT image.
It will be used in implemen
With the OCRAM expanded to 256KB and the SPL_PINCTRL enabled with
-u-boot.dtsi entries to include the pinmuxing in SPL, the manual
code setting up the pinmux can go away.
This patch removes the legacy pinmuxing code from the board file.
Signed-off-by: Adam Ford
diff --git a/board/logicpd/imx6/i
With the 256KB of OCRAM available to SPL now, there should be
enough room to enable the pinmuxing in SPL from the device tree.
This patch enables SPL_PINCTRL et al and adds the serial and
usdhc pin mux references to the -u-boot.dtsi file so the pins can be
configured from the device tree.
Signed-
Since this board config only supports, the i.MX6D/i.MX6Q configurations,
256K of on-chip RAM is available which increases the space available
to SPL to help further reduce board code and further enable device tree
functions.
This patch enables 256K of RAM.
Signed-off-by: Adam Ford
diff --git a/
On 10/9/19 9:19 AM, AKASHI Takahiro wrote:
This patch will lift the upper limit of maximum path length.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Heinrich Schuchardt
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boo
On 10/9/19 9:19 AM, AKASHI Takahiro wrote:
There is no practical reason to set a maxmum length of text either for
file path or whole device path in device path-to-text conversion.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_device_path_to_text.c | 90 +---
1 fil
On Wed, 2019-10-09 at 09:47 +0800, Bin Meng wrote:
> On Wed, Oct 9, 2019 at 9:15 AM Atish Patra
> wrote:
>
> nits: please remove the ending period in the commit summary
>
> > The release linux boot image header in v5.3 is different from the
>
> nits: Linux
>
> > one present in U-boot. Align th
The released Linux boot image header in v5.3 is different from the
one present in U-Boot. Align the header with the new version. The
changes in Linux are backward compatible. Previous U-Boot releases
with older header will continue to work as well. As v5.3 kernel is
the first one to support image h
Am 09.10.2019 um 18:26 schrieb Tom Rini:
On Tue, Oct 08, 2019 at 10:48:39AM +0200, Michal Simek wrote:
Hi Tom,
On 19. 09. 19 15:28, Michal Simek wrote:
On 13. 09. 19 17:09, Tom Rini wrote:
On Wed, Sep 11, 2019 at 03:39:53PM +0200, Michal Simek wrote:
From: T Karthik Reddy
This patch uses
On 10/9/19 9:19 AM, AKASHI Takahiro wrote:
device_path strcuture has 2 bytes of "length" field, and so
file path length should not exceed this limit, 65535.
Signed-off-by: AKASHI Takahiro
Thanks for the patch.
Reviewed-by: Heinrich Schuchardt
__
On Tue, Oct 8, 2019 at 7:00 PM Emmanuel Vadot wrote:
>
> rk3328 can use same-as-spl option so next loaders are loaded from the same
> medium.
> Add the boot order in the rock64 dts otherwise booting from sdcard
> will result in u-boot looking into the eMMC.
>
> Signed-off-by: Emmanuel Vadot
Revie
On 10/09/2019 07:25 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
>
> On 09-Oct-19 9:20 PM, tudor.amba...@microchip.com wrote:
>> Hi, Vignesh,
>>
>> On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
>>> External E-Mail
>>>
>>>
>>> Hi Tudor,
>>>
>>> On 01/10/19 2:29 PM, tudor.amba...@mi
On Tue, Oct 08, 2019 at 10:48:39AM +0200, Michal Simek wrote:
> Hi Tom,
>
> On 19. 09. 19 15:28, Michal Simek wrote:
> > On 13. 09. 19 17:09, Tom Rini wrote:
> >> On Wed, Sep 11, 2019 at 03:39:53PM +0200, Michal Simek wrote:
> >>
> >>> From: T Karthik Reddy
> >>>
> >>> This patch uses auto instea
On 09-Oct-19 9:20 PM, tudor.amba...@microchip.com wrote:
> Hi, Vignesh,
>
> On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
>> External E-Mail
>>
>>
>> Hi Tudor,
>>
>> On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
>>> From: Tudor Ambarus
>>>
>>> JESD216 allow vendors to define thei
Hi, Vignesh,
On 10/01/2019 11:59 AM, Tudor Ambarus - M18064 wrote:
> @@ -1892,6 +1921,12 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
> dev_info(dev, "non-uniform erase sector maps are not
> supported yet.\n");
> break;
>
> + case
Hi Giulio,
On Wed, Oct 9, 2019 at 12:59 PM Giulio Benetti
wrote:
>
> Hi Fabio and Stefano,
>
> On 9/29/19 9:40 PM, Fabio Estevam wrote:
> > We try to use DM in U-Boot proper as much as possible, but using DM in
> > SPL is currently not a requirement, especially due to internal RAM
> > size constr
Hi Fabio and Stefano,
On 9/29/19 9:40 PM, Fabio Estevam wrote:
We try to use DM in U-Boot proper as much as possible, but using DM in
SPL is currently not a requirement, especially due to internal RAM
size constraints.
IOMUXC and LPUART(using 24Mhz clock) work correctly using DM.
About clk dri
Hi, Vignesh,
On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Hi Tudor,
>
> On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
>> From: Tudor Ambarus
>>
>> JESD216 allow vendors to define their own SFDP tables.
>>
>> Add Microchip SFDP parser. The vendor table is
On Wed, Oct 9, 2019 at 10:23 AM Walter Lozano
wrote:
>
> Hi Adam
>
> On Tuesday, October 08, 2019 15:31 -03, Adam Ford wrote:
>
> > The pfuze100 is the PMIC connected to the I2C bus. Currently,
> > the I2C driver is disabled which prevents the PMIC from operating.
> >
> > This patch enables the
Add some helpers that can be called by the drivers to load the firmware
resource table from an elf32 / elf64 image.
The stm32 remoteproc driver makes use of it, to load the resource table before
the elf image itself.
This series applies on top of the "remoteproc: Add support for R5F and DSP
proces
Load the optional resource table from the firmware, and write its
address in the dedicated backup register.
Signed-off-by: Fabien Dessenne
---
drivers/remoteproc/stm32_copro.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc
When the coprocessor has been started, provide the context to Linux
kernel so it can handle it:
- update the coprocessor node of kernel DeviceTree with the
"early-booted" property.
- write the resource table address in a dedicated backup register.
Signed-off-by: Fabien Dessenne
---
board/st/st
The .is_running() ops expects a return value of 0 if the processor is
running, 1 if not running : align to this.
Signed-off-by: Fabien Dessenne
---
drivers/remoteproc/stm32_copro.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/
Use the backup register #17 as coprocessor resource table address.
Signed-off-by: Fabien Dessenne
---
arch/arm/mach-stm32mp/include/mach/stm32.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h
b/arch/arm/mach-stm32mp/include/mach/stm32.h
index b3e9
Add rproc_elf_load_rsc_table(), which searches for a resource table in
an elf64/elf32 image, and if found, copies it to device memory.
Add also the elf32 and elf64 variants of this API.
Add a test for this.
Signed-off-by: Fabien Dessenne
---
drivers/remoteproc/rproc-elf-loader.c | 269 ++
On Tue, Oct 8, 2019 at 7:50 PM Peng Fan wrote:
>
> > > +
> > > +Build U-Boot
> > > +
> > > +$ export CROSS_COMPILE=aarch64-poky-linux- $ make
> > > +imx8mm_evk_defconfig $ export ATF_LOAD_ADDR=0x92 $ make
> > flash.bin
> >
> > Build fails due to default_serial_console undefined. D
Hi Anatolij,
Gentle ping, did you have time to review this patchset ?
Thanks,
Neil
On 30/08/2019 14:09, Neil Armstrong wrote:
> Synchronize the Amlogic Meson Video driver back with the latest
> DRM misc tree, adding G12A platform support, from the latest commit:
> 528a25d040bc ("drm: meson: use m
Build the keystone 3 platforms with the keystone 2 platforms, in order
to get back more room in the "catch-all" build jobs.
Signed-off-by: Tom Rini
---
.travis.yml | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index ebe849f9909c..caad1ee33d
As both "catch-all" ARM jobs are nearing their time limit, move all of
the bcm SoC boards into a single job.
Signed-off-by: Tom Rini
---
.travis.yml | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index c48b711659e9..ebe849f9909c 100644
--- a/
Hi,
On 02/10/19 15:39, Michal Simek wrote:
> From: Ibai Erkiaga
>
> zynqmp-power driver for ZynqMP to handle the communication with the PMU
> firmware. Firmware driver just probes subnodes and power driver handles
> communication with PMU using the IPI mailbox driver.
>
> Signed-off-by: Ibai Er
Hi Ibai, Michal,
I had half-written a review of this patch and patch 4. Unfortunately I
didn't finish them before they got applied. I'll send them now anyway,
they are mostly nitpicking but you might consider them for a future
improvement. Sorry for the inconvenience.
On 02/10/19 15:39, Michal S
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> Add a field to the PCI emulator per-device data which records which device
> is being emulated. This is useful when the emulator needs to check the
> device for something.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/pci/pci-emul-uclass
Hi Simon,
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> In TPL we try to minimise code size so do not include the PCI subsystem.
> We can use fixed BARs and drivers can directly program the devices that
> they need.
>
> However we do need to bind the devices on the PCI bus and without P
From: Zumeng Chen
This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.
Signed-off-by: Zumeng Chen
Signed-off-by: Quanyang Wang
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-7000.dtsi | 158 +++
From: Andreas Färber
Derived from odroid-n2_defconfig and README.odroid-n2.
Reviewed-by: Neil Armstrong
Signed-off-by: Andreas Färber
Signed-off-by: Neil Armstrong
---
board/amlogic/w400/MAINTAINERS| 1 +
board/amlogic/w400/README.khadas-vim3 | 132 ++
confi
From: Andreas Färber
Write SoC instead of Soc. The Linux driver is not affected.
Fixes: f41d723b9f ("ARM: meson: display Amlogic SoC Information")
Signed-off-by: Andreas Färber
Signed-off-by: Neil Armstrong
---
arch/arm/mach-meson/board-info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Hi Andreas,
This is a resend from v2 with first patch resync'ed on v5.4-rc2.
This mini-series adds initial support for Amlogic A311D based Khadas VIM3.
v2 fixes an oversight and adds some cleanups.
v2 -> v3:
* Resync patch 1 on v5.4-rc2
* Removed bad signeoff of Julien Masson in patch 3
v1 ->
From: Andreas Färber
Values imported from Linux driver, but in correct numeric order.
Khadas VIM3 prints: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
Cc: Christian Hewitt
Signed-off-by: Andreas Färber
Signed-off-by: Neil Armstrong
---
arch/arm/mach-meson/board-info.c | 1 +
1 file chang
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> At present when these fail to boot there is no message, just a hang. Add a
> panic so it is obvious that something when wrong.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/lib/spl.c | 2 +-
> arch/x86/lib/tpl.c | 2 +-
> 2 files change
Hi Simon,
On Wed, Sep 25, 2019 at 10:58 PM Simon Glass wrote:
>
> The x86 power unit handles power management. Support initing this device
> which is modelled as a new type of system controller since there are no
> operations needed.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm
Hi Simon,
On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
>
> On x86 platforms the SPI flash can be mapped into memory so that the
> contents can be read with normal memory accesses.
>
> Add a new SPI flash method to find the location of the SPI flash in
> memory. This differs from the existi
Hi Simon,
On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
>
> At present SPI-flash testing relies on a sandbox driver which emulates the
> SPI bus and implements a flash chip behind that emulated bus.
>
> This provides good coverage but can only implement features supported by
> the SPI bus.
On Wed, Oct 9, 2019 at 2:57 PM Dalon L Westergreen
wrote:
>
> On Sat, 2019-10-05 at 21:40 +0200, Simon Goldschmidt wrote:
>
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
> >
>
>
> Stratix10 requires a hex image of the spl plus s
On Wed, Oct 9, 2019 at 2:56 PM Dalon L Westergreen
wrote:
>
> On Sat, 2019-10-05 at 21:41 +0200, Simon Goldschmidt wrote:
>
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
> >
>
>
> CONFIG_OF_EMBED was primarily enabled to support
On Tue, Oct 08, 2019 at 12:38:57PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following watchdog related patches:
>
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Oct 08, 2019 at 06:56:05AM +, eugen.hris...@microchip.com wrote:
> Hello Tom,
>
> Please pull tag u-boot-atmel-2020.01-a , the first set of new features
> for the 2020.01 release
>
> The feature set includes support for two new boards from Microchip AT91:
> The sama5d27_wlsom1_ek ,
On Tue, Oct 08, 2019 at 04:28:33PM +0800, Bin Meng wrote:
> Hi Tom,
>
> This PR includes the following changes for v2020.01:
>
> - Rename existing FSP code to fsp1
> - Add fsp2 directory in preparation to support FSP 2.0
> - Various x86 platform codes update
> - Various bug fixes and updates in
On Sun, Oct 06, 2019 at 11:13:21PM +0200, Heinrich Schuchardt wrote:
> The following changes since commit dac51e9aaf6fd38298007b266feb6a80e9ec91ee:
>
> Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-10-05
> 20:06:58 -0400)
>
> are available in the Git repository at:
>
> https://
Hi Simon,
On Wed, Sep 25, 2019 at 10:12 PM Simon Glass wrote:
>
> This provides access to SPI flash both through a read-only memory map and
> with operations to erase and write flash. It supports 4KB or 64KB erase
> sizes.
>
I read the SPI controller chapter in the datasheet of apollolake as
wel
On Sat, 2019-10-05 at 21:40 +0200, Simon Goldschmidt wrote:
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
> > From: Dalon Westergreen
> > Stratix10 requires a hex image of the spl plus spl devicetree offset tothe
> > Stratix10 onchip memory located at SPL_TEXT_BASE. This patch addsa target
On Sat, 2019-10-05 at 21:41 +0200, Simon Goldschmidt wrote:
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
> > From: Dalon Westergreen
> > CONFIG_OF_EMBED was primarily enabled to support the stratix10spl hex file
> > requirements. Since this option now produces awarning during build, and th
Hi Tudor,
On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
> From: Tudor Ambarus
>
> JESD216 allow vendors to define their own SFDP tables.
>
> Add Microchip SFDP parser. The vendor table is allocated using
> resource-managed kmalloc - the table will be freed on driver detach.
> It will
Signed-off-by: liuhao
---
MAINTAINERS | 6 +++
arch/arm/Kconfig | 8
arch/arm/dts/Makefile| 2 +
arch/arm/dts/phytium-ft2004.dts | 33 ++
board/phytium/ft2004/Kconfig | 12 +
board/phytium/ft2004/MAINTAINERS | 8
On Wed, Oct 9, 2019 at 11:08 AM Kever Yang wrote:
>
> We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
> and when we introduce the TPL, the SPL space is in DRAM, we reserve
> space to avoid SPL text overlap with ATF bl31.
>
> Now we decide to move ATF entry point to 0x4 i
Hi Eugeniy,
On 07/10/19 8:16 PM, Eugeniy Paltsev wrote:
> Hi Vignesh,
>
> I've tested your "[U-Boot,RFT,v2,0/3] spi-nor: spi-nor-ids: Fix 4 Byte
> addressing " series
> applies on the latest master (879396a2405).
> 'axs103_defconfig' was used without changes.
> > Probe/read/write/erase work for
hi
I am a bit confused about two things
1) is the "ide" (disk read/write/boot) module intended to be PCI-MEM
"memory-mapped" oriented concerning the harddrive? or is it PCI_IO
oriented? there are too many layers of code and this makes me confused
2) what is the philosophy about initializing the PCI
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