TheOn 1/14/19 10:38 PM, Simon Goldschmidt wrote:
> This fixes CVE-2018-18439 ("insufficient boundary checks in network
> image boot") by using lmb to check for a valid range to store
> received blocks.
>
> Signed-off-by: Simon Goldschmidt
> Acked-by: Joe Hershberger
> ---
Hello Simon,
due to t
There are 3 supported modes of operation:
1) Show version
2) List image contents
3) Extract image component
Option (1) terminates early, so only options (2) and (3) remain. Remove
redundant check for these modes.
Signed-off-by: Martyn Welch
---
tools/dumpimage.c | 85 +
The utility dumpimage has error paths that display the usage and others
that exit without displaying usage. Add an explicit help option to
dumpimage to display the usage and remove it's use in error paths to make
the error messages more obvious and errors paths more consistent.
Signed-off-by: Mart
Help message isn't clear over the use of the "-T" option (it's to declare
the type of image that the tool is operating on), which also is optional
as it defaults to the default image type. It's also missing a description
of the "-o" option, so add it.
Signed-off-by: Martyn Welch
---
tools/dump
The dump image utility has very confusing syntax. If called to list image
contents ("-l") it takes the image name as a positional argument. If the
utility is called to extract something from the image, the image must be
provided via the optional argument "-i" as well as the positional argument
but
The dumpimage utility errors out in a number of places without providing
sufficient feedback to allow the user to easily determine what they have
done wrong. Add addtional error messages to make the cause of the failure
more obvious.
Signed-off-by: Martyn Welch
---
tools/dumpimage.c | 11 ++
On Fri, 25 Jan 2019, Chris Spencer wrote:
Thanks for a reply. The problem here is not with leftover descriptors -- it
is MDIO bus not working at all. It is either bogus speed/clock in DM mode or
something else that I haven't found yet. Reading all zeroes means there is
no communication with the P
On Fri, Jan 25, 2019 at 12:47 AM Jagan Teki wrote:
>
> Like other Allwinner A64 boards, pinebook also need altering
> auto-numbering of mmc2 to mmc1 which is available in common
> sunxi dsti file, sunxi-u-boot.dtsi
>
> Pinebook has a separate sun50i-a64-pinebook-u-boot.dtsi which
> takes more prec
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.
Signed-off-
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
Signed-off-by: Vladimir Oltean
---
Changes in v3:
* Patch added in this version.
drivers/net/phy/atheros.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/phy/atheros.
Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.
Signed-off-by: Vladimir Oltean
---
Changes in v3:
* Patch added in this version. Partially squashed with patch 1/3 from v2,
since addressing the comments on that patch gave its commit message
a new m
Delete the extraneous write to debug reg 5 that enables Tx delay
When the driver was originally introduced in commit "6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.
Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID
and
Signed-off-by: Vladimir Oltean
---
Changes in v3:
* Removed access to magic register 0x5 which turned out to be duplicated code
with unwanted consequences. Broke that out into separate patch (2/6).
drivers/net/phy/atheros.c | 69 ---
1 file changed
The patchset adds support for disabling a PHY feature that may cause packet
loss, and also cleans up the atheros.c driver a bit.
As part of the cleanup, there are also some functional changes for the AR8035
in the RGMII internal delay area. Due to a mistake, RGMII Tx internal delay
used to be impl
According to the AR8031 and AR8035 datasheets, smartEEE mode
(active by default) makes the PHY enter sleep after a configurable
idle time. It does this autonomously, without LPI (Low Power Idle)
signals coming from MAC. AR8021 does not appear to support this.
This patch allows disabling the SmartE
On Fri, 25 Jan 2019 at 19:21, Heinrich Schuchardt wrote:
>
> On 1/23/19 6:33 PM, Alexander Graf wrote:
> > While discussing something compeltely different, Ard pointed out
> > that it might be legal to omit calling SetVirtualAddressMap altogether.
> >
> > While that sounds great, we currently rely
On Thu, Jan 24, 2019 at 7:19 AM Felix Brack wrote:
>
> Hello Adam,
>
> On 23.01.2019 22:13, Adam Ford wrote:
> > By removing EXT support from SPL, it makes room for the extra
> > overhead of enabling OF_CONTROL in SPL. With SPL_OF_CONTROL
> > enabled, extra options need to be added to the device
This adds reset handling to the devicetree-enabled denalid nand driver.
For backwards compatibility, only a warning is printed when failing to
get reset handles.
Signed-off-by: Simon Goldschmidt
---
drivers/spi/cadence_qspi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers
This commit removes ad-hoc reset handling for peripheral resets from SPL
for socfpga gen5.
This is done because as U-Boot drivers support reset handling by now.
For kernels that don't support taking peripherals out of reset that are
not enabled by U-Boot, a new Kconfig option "OLD_SOCFPGA_KERNEL_
To clean up reset handling for socfpga gen5, let's move the code snippet
taking the DDR controller out of reset from SPL to the DDR driver.
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/spl_gen5.c | 1 -
drivers/ddr/altera/sdram_gen5.c | 4
2 files changed, 4 insertions(+), 1
This adds reset handling to the devicetree-enabled denalid nand driver.
For backwards compatibility, only a warning is printed when failing to
get reset handles.
Signed-off-by: Simon Goldschmidt
---
drivers/mtd/nand/raw/denali_dt.c | 8
1 file changed, 8 insertions(+)
diff --git a/dr
The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
some device tree nodes are missing reset handles.
Since the socfpga gen5 devicetrees are currently in sync with Linux 4.20,
and these reset handles are not ad
This series implements peripheral reset handling for socfpga gen5.
It moves from enabling all peripherals during SPL startup to using the
socfpga reset driver from all peripherals and enabling peripherals when
they are used.
As Linux cannot even handle this in 4.20, a Kconfig option is added to
k
On Thu, Jan 24, 2019 at 6:35 PM Vladimir Oltean wrote:
>
> On 1/24/19 8:20 AM, Joe Hershberger wrote:
> > On Wed, Jan 23, 2019 at 5:47 PM Vladimir Oltean
> > wrote:
> >> static int ar8021_config(struct phy_device *phydev)
> >> {
> >> phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
On Thu, Jan 24, 2019 at 6:35 PM Vladimir Oltean wrote:
>
> On 1/24/19 8:16 AM, Joe Hershberger wrote:
> > On Wed, Jan 23, 2019 at 5:46 PM Vladimir Oltean
> > wrote:
> >>
> >> Signed-off-by: Vladimir Oltean
> >> ---
> >> Changes in v2:
> >> * Patch added in this version.
> >>
> >> drivers/ne
This unbreaks dfu mmc_file_op which is currently broken since using the
load cmd on a buffer from heap is not allowed - added with
commit aa3c609e2be5 ("fs: prevent overwriting reserved memory")
Fixes: commit aa3c609e2be5 ("fs: prevent overwriting reserved memory")
Reported-by: Stephen Warren
Sig
On 1/23/19 6:33 PM, Alexander Graf wrote:
> While discussing something compeltely different, Ard pointed out
> that it might be legal to omit calling SetVirtualAddressMap altogether.
>
> While that sounds great, we currently rely on that call to remove
> all function pointers to code that we do no
+Vignesh
Hi Cédric,
On Fri, 25 Jan 2019 18:28:02 +0100
Cédric Le Goater wrote:
> Hello
>
> On 10/10/18 2:02 PM, Cédric Le Goater wrote:
> > Hello Boris,
> >
> > On 10/10/18 9:32 AM, Boris Brezillon wrote:
> >> Hi Cédric,
> >>
> >> On Wed, 10 Oct 2018 11:46:56 +0530
> >> Jagan Teki wrote:
>
Hello
On 10/10/18 2:02 PM, Cédric Le Goater wrote:
> Hello Boris,
>
> On 10/10/18 9:32 AM, Boris Brezillon wrote:
>> Hi Cédric,
>>
>> On Wed, 10 Oct 2018 11:46:56 +0530
>> Jagan Teki wrote:
>>
>>> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater wrote:
On 10/4/18 5:57 PM, Jagan Teki w
This adds initial support for micro-DPU (uDPU) board which is based on
Armada-3720 SoC.
micro-DPU is the single-port FTTdp "distribution point unit" made by Methode
Electronics
which offers complete modularity with replaceable SFP modules both for uplink
and downlink
(G.hn over twisted-pair, G.h
On Thu, Jan 10, 2019 at 02:05:57PM -0600, Doug Zobel wrote:
> Driver for the TI LP5562 4 channel LED controller. Supports
> independent on/off control of all 4 channels. Supports LED_BLINK
> on 3 independent channels: blue/green/red. The white channel can
> blink, but shares the blue channel bl
On Fri, Jan 25, 2019 at 07:48:42PM +0530, Vignesh R wrote:
> Merge drivers/soc/keystone/ into drivers/soc/ti/
> and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.
>
> Signed-off-by: Vignesh R
Thanks for adding this in. Small change please:
> diff --git a/include/configs/ti_armv7_keystone2.h
On Fri, Jan 25, 2019 at 07:48:38PM +0530, Vignesh R wrote:
> From: Grygorii Strashko
>
> Texas Instruments' System Control Interface (TI-SCI) Message Protocol
> abstracts management of NAVSS resources, like PSI-L pairing and
> unpairing, UDMAP tx/rx/flow configuration and Rings.
>
> This patch
On Fri, Jan 25, 2019 at 01:44:27AM +0530, Jagan Teki wrote:
> Hi Tom,
>
> Please pull this PR.
>
> thanks,
> Jagan.
>
> The following changes since commit f83ef0dac83110d20389eb71f09285f009f3d198:
>
> Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips
> (2019-01-17 19:12:55 -
On Thu, Jan 24, 2019 at 11:35:57AM -0600, Joe Hershberger wrote:
> Hi Tom,
>
> Passed the travis build...
> https://travis-ci.org/jhershbe/u-boot/builds/483483372
>
> The following changes since commit aff66f22d6eeb27c6329c0a3c1ebc52914c8affa:
>
> Merge tag 'mips-pull-2019-01-23' of git://gi
On Thu, Jan 24, 2019 at 04:25:27PM +, York Sun wrote:
> Tom,
>
> The following changes since commit 7794fe2c8c1303d303dbc515955c6c5be706da88:
>
> Merge git://git.denx.de/u-boot-nds32 (2019-01-22 22:00:20 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-mp
On Thu, Jan 24, 2019 at 4:11 PM Frank Wunderlich
wrote:
>
> Hi,
>
> i ran also in same problem, after resize environment (4k to 8k), because my
> 4k is no more enough for my environment.
>
> i did not understand my CRC have to be checked if i want to save (and the
> checked part will be overridd
On Fri, Jan 25, 2019 at 08:11:11PM +0530, Vignesh R wrote:
> On 04/12/18 2:15 PM, Vignesh R wrote:
> > Completely move CONFIG_SPI_FLASH from remaining board header files to
> > defconfigs
> >
> > Signed-off-by: Vignesh R
> > ---
> > Done with the help of moveconfig.py. Compile tested on travis-c
There is a build issue with this series (forgot to run buildman on
this), I'll send a v2 shortly.
On 24/01/2019 15:42, Jean-Jacques Hiblot wrote:
Enable DM_USB support in u-boot and in SPL.
This brings this configuration closer to am43xx_evm_defconfig.
Signed-off-by: Jean-Jacques Hiblot
---
On 25/01/19 8:17 PM, Jagan Teki wrote:
> On Fri, Dec 21, 2018 at 12:18 PM Vignesh R wrote:
>>
>> SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
>> SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
>> enums yield no user and therefore support seems to b
On Fri, Jan 25, 2019 at 03:40:35PM +0100, Jean-Jacques Hiblot wrote:
>
> On 15/01/2019 15:28, Tom Rini wrote:
> >On Tue, Jan 08, 2019 at 06:16:31PM +0530, Faiz Abbas wrote:
> >
> >>With DM conversion completed, enable CONFIG_BLK for a
> >>few pending TI boards.
> >>
> >>Signed-off-by: Faiz Abbas
On Fri, Dec 21, 2018 at 12:18 PM Vignesh R wrote:
>
> SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
> SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
> enums yield no user and therefore support seems to be incomplete. Remove
> these configs so as to a
On 15/01/2019 15:28, Tom Rini wrote:
On Tue, Jan 08, 2019 at 06:16:31PM +0530, Faiz Abbas wrote:
With DM conversion completed, enable CONFIG_BLK for a
few pending TI boards.
Signed-off-by: Faiz Abbas
Reviewed-by: Lokesh Vutla
---
configs/am335x_boneblack_vboot_defconfig | 1 -
configs/a
On 04/12/18 2:15 PM, Vignesh R wrote:
> Completely move CONFIG_SPI_FLASH from remaining board header files to
> defconfigs
>
> Signed-off-by: Vignesh R
> ---
> Done with the help of moveconfig.py. Compile tested on travis-ci:
> https://travis-ci.org/r-vignesh/u-boot/builds/463155999
>
Gentle
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Friday, January 4, 2019 10:56 PM
> To: Ooi, Joyce ; Joe Hershberger
>
> Cc: See, Chin Liang ; Ong, Hean Loong
> ; Priyanka Jain ; u-
> b...@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v3] net: phy: add TSE PCS support
On 23/01/19 7:26 PM, Tom Rini wrote:
> On Wed, Jan 23, 2019 at 07:13:11PM +0530, Vignesh R wrote:
>> Tom,
>>
>> On 23/01/19 4:05 PM, Peter Ujfalusi wrote:
>>> Tom,
>>>
>>> On 22/01/2019 20.56, Tom Rini wrote:
On Tue, Jan 22, 2019 at 08:33:57PM +0530, Vignesh R wrote:
> The UDMA-P is
From: Grygorii Strashko
Add DT node for MCU NAVSS its components to get DMA working on AM654
SoC.
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 46
1 file changed, 46 insertions(+)
diff
From: Grygorii Strashko
Enable TI K3 AM65x PSI-L, Ring Accelerator and UDMA drivers
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
configs/am65x_evm_a53_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/am65x_evm_a53
The UDMA-P is intended to perform similar (but significantly upgraded) functions
as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
supports the transmission and reception of various packet types.
The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
chan
Merge drivers/soc/keystone/ into drivers/soc/ti/
and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig.
Signed-off-by: Vignesh R
---
arch/arm/mach-keystone/Kconfig | 8
drivers/soc/Makefile | 1 -
drivers/soc/keystone/Makefile | 3
From: Grygorii Strashko
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.
This patch adds support for requesting and configuring such resources
from TI-SCI fir
This series adds DMA support for TI's AM654 SoC.
v2:
Align DT bindings with latest proposed bindings as pointed out by Peter.
Merge drivers/soc/keystone into drivers/soc/ti
Background:
The AM65x TRM (http://www.ti.com/lit/pdf/spruid7b) describes the Data Movement
Architecture which is implmented
From: Grygorii Strashko
Add TI Communications Port Programming Interface (CPPI) 5
interface description and helpers
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
include/linux/soc/ti/cppi5.h | 995 +++
1 file changed, 995
From: Grygorii Strashko
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
The RINGACC converts constant-address read and write accesses to equiva
Le 2019-01-15 13:53, Alexandre GRIVEAUX a écrit :
Hello,
I tried to have mainline uboot for Z-turn board (patch sent in
December, wrong window: [PATCH] ARM: zynq: Adding ps7_init_gpl.c for
Z-turn board)
Even with the right ps7_init_gpl.c : the board doesn't boot.
I tried to correct zynq-zturn.d
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms.
Signed-off-by: Rajesh Bhagat
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8
include/configs/ls1012a_common.h | 1 -
include/configs/ls1043a_common.h | 1 -
include/configs/ls1046a_common.h | 1 -
in
On 25.01.2019 12:12, Carlo Caione wrote:
> On 24/01/2019 20:48, Vladimir Oltean wrote:
>> On 1/24/19 10:19 PM, Carlo Caione wrote:
>>> On 24/01/2019 20:12, Vladimir Oltean wrote:
>>
>> I can't completely answer that, TBH I don't even know who is supposed to
>> make that distinction.
>
> In th
On 25.01.19 13:13, Michal Simek wrote:
> On 25. 01. 19 13:00, Alexander Graf wrote:
>>
>>
>> On 25.01.19 12:56, Michal Simek wrote:
>>> On 25. 01. 19 12:25, Alexander Graf wrote:
On 24.01.19 16:31, Michal Simek wrote:
> From: Siva Durga Prasad Paladugu
>
> This patch a
From: Marcel Ziswiler
Calling sata_scan() with a null pointer probably won't make much sense.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Simon Glass
---
Changes in v2:
- Added Simon's reviewed-by.
cmd/sata.c | 4
1 file changed, 4 insertions(+)
diff --git a/cmd/sata.c b/cmd/sata.c
i
On 24.01.19 12:04, AKASHI Takahiro wrote:
> "env [print|set] -e" allows for handling uefi variables without
> knowing details about mapping to corresponding u-boot variables.
>
> Signed-off-by: AKASHI Takahiro
> ---
> MAINTAINERS | 1 +
> cmd/Kconfig | 6 +
> cmd/Makefile
crashing in case no SATA driver is actually there:
Apalis iMX6 # sata init
data abort
pc : [<8ff78e1a>] lr : [<8ff78e1b>]
reloc pc : [<1781be1a>]lr : [<1781be1b>]
sp : 8df53068 ip : 0001 fp : 0002
r10: 8df612e8 r9 : 8df5ceb0 r8 : 8ffc2b28
r7 : 8ff746ed r6 :
From: Marcel Ziswiler
While uclass_find_device() fails with -ENODEV in case of list_empty
strangely uclass_find_first_device() returns 0.
Fix uclass_find_first_device() to also fail with -ENODEV instead.
Signed-off-by: Marcel Ziswiler
---
Changes in v2:
- Update dm_test_uclass_devices_find()
On 24. 01. 19 18:24, Joe Hershberger wrote:
> On Thu, Jan 24, 2019 at 2:07 AM Michal Simek wrote:
>>
>> On 23. 01. 19 19:20, Joe Hershberger wrote:
>>> On Tue, Nov 27, 2018 at 12:20 AM Siva Durga Prasad Paladugu
>>> wrote:
This patch adds support for gmiitorgmii converter.
This con
On 25. 01. 19 13:00, Alexander Graf wrote:
>
>
> On 25.01.19 12:56, Michal Simek wrote:
>> On 25. 01. 19 12:25, Alexander Graf wrote:
>>>
>>>
>>> On 24.01.19 16:31, Michal Simek wrote:
From: Siva Durga Prasad Paladugu
This patch adds distro boot commands for qspi and nand. The
>>>
Hi Adam,
On 24/01/2019 21:33, Adam Ford wrote:
The OMAP36 and DM37 TRM state to disable extneded drain IO before
changing the PBIAS. This patch does this before pmic writes if
the CONFIG_MMC_OMAP36XX_PINS flag is set and the cpu family is
omap36xx
I believe things could be done without all th
On 25.01.19 12:56, Michal Simek wrote:
> On 25. 01. 19 12:25, Alexander Graf wrote:
>>
>>
>> On 24.01.19 16:31, Michal Simek wrote:
>>> From: Siva Durga Prasad Paladugu
>>>
>>> This patch adds distro boot commands for qspi and nand. The
>>> distro boot commands now reads the script from flash of
On 24.01.19 12:04, AKASHI Takahiro wrote:
> This patch set is a collection of patches to enhance efi user interfaces
> /commands. It will help improve user experience on efi boot and make it
> more usable *without* edk2's shell utility.
>
> Let's see how it works:
> => efidebug boot add 1 SHELL
On 25. 01. 19 12:25, Alexander Graf wrote:
>
>
> On 24.01.19 16:31, Michal Simek wrote:
>> From: Siva Durga Prasad Paladugu
>>
>> This patch adds distro boot commands for qspi and nand. The
>> distro boot commands now reads the script from flash offset
>> of 63.5MB and executes it.
>>
>> Setup d
On 25. 01. 19 12:23, Alexander Graf wrote:
>
>
> On 24.01.19 16:31, Michal Simek wrote:
>> This patch is doing two things.
>> 1. Exchanging order of boot commands. distro_bootcmd is run first
>> followed by Xilinx boot command.
>> 2. Remove CONFIG_BOOTCOMMAND from configs (and follow mainline) by
On Fri, 25 Jan 2019 19:42:22 +0800
Chen-Yu Tsai wrote:
> On Fri, Jan 25, 2019 at 7:37 PM Andre Przywara
> wrote:
> >
> > On Fri, 25 Jan 2019 19:01:12 +0800
> > Chen-Yu Tsai wrote:
> >
> > Hi,
> >
> > > On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> > > wrote:
> > > >
> > > > On Fri, Jan 25,
On Fri, Jan 25, 2019 at 7:37 PM Andre Przywara wrote:
>
> On Fri, 25 Jan 2019 19:01:12 +0800
> Chen-Yu Tsai wrote:
>
> Hi,
>
> > On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> > wrote:
> > >
> > > On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai
> > > wrote:
> > > >
> > > > On Fri, Jan 25, 2019 at 4:
On Fri, Jan 25, 2019 at 5:07 PM Andre Przywara wrote:
>
> On Fri, 25 Jan 2019 19:01:12 +0800
> Chen-Yu Tsai wrote:
>
> Hi,
>
> > On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> > wrote:
> > >
> > > On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai
> > > wrote:
> > > >
> > > > On Fri, Jan 25, 2019 at 4:
On Fri, 25 Jan 2019 19:01:12 +0800
Chen-Yu Tsai wrote:
Hi,
> On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki
> wrote:
> >
> > On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai
> > wrote:
> > >
> > > On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki
> > > wrote:
> > > >
> > > > On Tue, Jan 22, 2019 at 7:55
Hi Simon
On Fri, 2019-01-25 at 09:18 +1300, Simon Glass wrote:
> Hi Marcel,
>
> On Fri, 25 Jan 2019 at 03:30, Marcel Ziswiler
> wrote:
> > From: Marcel Ziswiler
> >
> > Given ahci_get_ops() being a macro not checking anything make sure
> > we
> > only call it if we do indeed have a dev pointer
On 24.01.19 16:31, Michal Simek wrote:
> From: Siva Durga Prasad Paladugu
>
> This patch adds distro boot commands for qspi and nand. The
> distro boot commands now reads the script from flash offset
> of 63.5MB and executes it.
>
> Setup default location via script_offset_f to 63.5MB to match
Hi Simon
On Fri, 2019-01-25 at 09:18 +1300, Simon Glass wrote:
> Hi Marcel,
>
> On Fri, 25 Jan 2019 at 03:30, Marcel Ziswiler
> wrote:
> > From: Marcel Ziswiler
> >
> > While uclass_find_device() fails with -ENODEV in case of list_empty
> > strangely uclass_find_first_device() returns 0.
> >
On 24.01.19 16:31, Michal Simek wrote:
> This patch is doing two things.
> 1. Exchanging order of boot commands. distro_bootcmd is run first
> followed by Xilinx boot command.
> 2. Remove CONFIG_BOOTCOMMAND from configs (and follow mainline) by
> creating Xilinx distribution bootcommand and wirin
On Fri, Jan 25, 2019 at 6:41 PM Jagan Teki wrote:
>
> On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wrote:
> >
> > On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wrote:
> > > >
> > > > On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki
>
On Fri, 25 Jan 2019 13:54:50 +0530
Jagan Teki wrote:
> From: Andre Przywara
>
> Add the MMC clock gates and reset bits for all the Allwinner SoCs.
> This allows them to be used by the MMC driver.
>
> We don't advertise the mod clock yet, as this is still handled by the
> MMC driver.
>
> Signe
This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.
To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.
Signed-off-by: S
Now that the PCIe driver supports DM and DT parsing, enable the PCIe DT
nodes that are used by this board.
Signed-off-by: Stefan Roese
Cc: Dirk Eibach
Cc: Mario Six
Cc: Chris Packham
Cc: Phil Sutter
Cc: Marek Behún
Cc: VlaoMao
---
v3:
- No change
v2:
- New file
arch/arm/dts/armada-xp-the
This function will be used by the Marvell Armada XP/38x PCIe driver,
which is moved to DM right now. So let's extract the functionality
from pci_uclass_child_post_bind() to make it available.
Signed-off-by: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
---
v3:
- New patch, replaces "[PATCH] core: o
This patch sync's the PCIe DT nodes with the recent Linux v4.20 version.
This change makes it easier to reference specific PCIe nodes in the
board dts files to e.g. enable a PCIe port as this is now necessary with
the new DM PCI driver for these platforms.
Signed-off-by: Stefan Roese
Cc: Dirk Eib
On Fri, Jan 25, 2019 at 2:05 PM Chen-Yu Tsai wrote:
>
> On Fri, Jan 25, 2019 at 4:27 PM Jagan Teki wrote:
> >
> > On Tue, Jan 22, 2019 at 7:55 AM Chen-Yu Tsai wrote:
> > >
> > > On Mon, Jan 21, 2019 at 6:31 PM Jagan Teki
> > > wrote:
> > > >
> > > > Compared to previous version changes[1] this
The brand Sinovoip is used for Sinovoip's original VOIP products, while
the Bananapi brand is for the single board computers they produce. This
has been verified by Bananapi. Rename the board from "Sinovoip BPI M2
Plus" to "Bananapi M2 Plus". For the defconfig file, all lowercase is
used.
To suppo
As of commit aa8fee415f46 ("ARM: dts: sun8i: h3: Split out
non-SoC-specific parts of Bananapi M2 Plus") in the Linux kernel, the
device tree for the Bananapi M2+ has been split into a common dtsi file,
and an SoC-specific board device tree file that includes both the shared
dtsi file and the soc dt
This series adds support for the H5 variant of the Bananapi M2+, and
also renames the MAINTAINERS entry and defconfig for the Bananapi M2+
from its current name, Sinovoip BPI M2+.
Sinovoip is the brand name used for their own VOIP-related products,
while the brand name "Bananapi" should be used fo
As the H5 is pin compatible with the H3, vendors tend to upgrade their
existing H3 products with an H5 SoC swap. This is the case with the
Bananapi M2+ H5.
Add the following to support it:
- device tree file: synced from Linux v5.0-rc1,
- defconfig: copy of bananapi_m2_plus_h3_defconfig with
On 24/01/2019 20:48, Vladimir Oltean wrote:
On 1/24/19 10:19 PM, Carlo Caione wrote:
On 24/01/2019 20:12, Vladimir Oltean wrote:
I can't completely answer that, TBH I don't even know who is supposed to
make that distinction.
In the kernel that distinction is made by the driver itself, henc
From: Hou Zhiqiang
Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB.
Signed-off-by: Hou Zhiqiang
---
V3:
- No change
configs/lx2160ardb_tfa_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
in
From: Hou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: Hou Zhiqiang
---
V3:
- No change
arch/arm/dts/fsl-lx2160a.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.d
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V3:
- No change
include/configs/lx2160a_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 41931e5b53..19053b43a1 100644
--- a/include/configs/lx2160a_common.
From: Hou Zhiqiang
For PCIe controllers with SRIOV, MSIx table entries of all the VFs
are not accessible if BAR size is set to less than 8MB.
This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.
Signed-off-by: Hou Zhiqiang
---
V3:
- New patch.
drivers/pci/pcie_layerscape_gen4
From: Hou Zhiqiang
PCIe configuration access to non-existent function triggered
SERROR interrupt exception.
Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.
This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.
Signed-off-by: H
From: Hou Zhiqiang
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead
of PCIE_LAYERSCAPE.
Signed-off-by: Hou Zhiqiang
---
V3:
- No change
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape
From: Hou Zhiqiang
When LAYERSCAPE Gen4 PCIe controller is sending multiple split
completions and ACK latency expires indicating that ACK should
be send at priority. But because of large number of split
completions and FC update DLLP, the controller does not give
priority to ACK transmission. Thi
From: Hou Zhiqiang
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Bao Xiaowei
---
V3:
- Added EP DT node fixup.
drivers/pci/Makefile |
From: Hou Zhiqiang
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Bao Xiaowei
---
V3:
- Refactored the EP mode code.
dr
From: Hou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.
Signed-off-by: Hou Zhiqiang
---
V3:
- No change
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 12
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++
.
From: Hou Zhiqiang
The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.
Signed-off-by: Hou Zhiqiang
---
V3:
- No change
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl
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