On Thu, Jan 24, 2019 at 6:35 PM Vladimir Oltean <vladimir.olt...@nxp.com> wrote: > > On 1/24/19 8:20 AM, Joe Hershberger wrote: > > On Wed, Jan 23, 2019 at 5:47 PM Vladimir Oltean <vladimir.olt...@nxp.com> > > wrote: > >> static int ar8021_config(struct phy_device *phydev) > >> { > >> phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); > >> - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); > >> - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); > >> + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, > >> + AR803x_DEBUG_REG_5); > >> + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, > >> 0x3D47); > > > > While this patch is an improvement on the former state, can we add a > > comment on the magic number or define a constant? > > > I have no idea what 0x3D47 is, sorry. I couldn't find any public AR8021 > register map either. For the other PHYs in this family, debug register 5 > holds TX_CLK_DELAY at bit 8. No idea of the implications of writing the > other bits. Will act on the rest of your comments.
OK, thanks. > -Vladimir > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot