Signed-off-by: Otavio Salvador
---
include/configs/pico-imx6ul.h | 2 ++
include/configs/pico-imx7d.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 0fea2d65dd..8082b74c9c 100644
--- a/include/configs/pico-imx6ul.h
+++
After discussing with TechNexion about how its default setting, it is
better to install on the eMMC user partition by default, when using
DFU, so it works out of box for majority of users.
Signed-off-by: Otavio Salvador
---
include/configs/pico-imx6ul.h | 4 ++--
include/configs/pico-imx7d.h |
The btrfs implementation passes cache-unaligned buffers into the
block layer, which triggers cache alignment problems down in the
block device drivers. Align the buffers to prevent this.
Signed-off-by: Marek Vasut
Cc: Marek Behun
---
fs/btrfs/ctree.c | 24 +---
fs/btrfs/
Add PCI entry without compatible string and with a DT node only with
reg = <...> property into the DT. This is needed for the tests to
verify whether such a setup creates an U-Boot PCI device with the
DT node associated with it in udevice.node.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Tom
Add test which checks if a PCI device described in DT with an
entry and reg = <...> property, but without compatible string
results in a valid U-Boot PCI udevice with the udevice.node
populated with reference to this DT node. Also check if the
other PCI device without a DT node does not contain any
Reword the documentation to make it clear the compatible string is now
optional, yet still matching on it takes precedence over PCI IDs and
PCI classes.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Tom Rini
---
doc/driver-model/pci-info.txt | 14 +-
1 file changed, 9 insertions(+
The PCI controller can have DT subnodes describing extra properties
of particular PCI devices, ie. a PHY attached to an EHCI controller
on a PCI bus. This patch parses those DT subnodes and assigns a node
to the PCI device instance, so that the driver can extract details
from that node and ie. conf
Of CONFIG_OF_TRANSLATE is enabled, this function still returns
untranslated bogus results. Add the missing translation.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Tom Rini
---
drivers/core/ofnode.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/core/ofn
The code fails to check if ops is non-NULL before using it's members.
Add the missing check and while at it, flip the condition to make it
more obvious what is actually happening.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Tom Rini
---
drivers/pci/pci-uclass.c | 12 ++--
1 file cha
On 08/23/2018 11:43 PM, Priyanka Jain wrote:
> Some lsch3 based SoCs like lx2160a contains three
> serdes modules.
> Add support for third serdes protocol in lsch3
>
> Signed-off-by: Priyanka Jain
> ---
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> b/arch/arm/include/
On 08/23/2018 08:27 AM, York Sun wrote:
> On 08/22/2018 06:15 PM, ying.zhang22...@nxp.com wrote:
>> From: Zhang Ying-22455
>>
>> * Add mpc8xxx_gpio_plat for for Layerscape SoC
>> * Make the mpc8xxx driver capable of handling Layerscape Soc.
>>
>
>
> This looks weird. Why don't you rename mpc8x
Hi Mario,
On 21 September 2018 at 01:02, Mario Six wrote:
>
> Hi Simon,
>
> On Fri, Aug 17, 2018 at 2:52 PM Simon Glass wrote:
> >
> > Hi Mario,
> >
> > On 13 August 2018 at 00:09, Mario Six wrote:
> > > The regmap functions currently assume that all register map accesses
> > > have a data widt
On 08/09/2018 02:56 AM, Ran Wang wrote:
> add Kconfig option for U QUICC Engine.
>
> Signed-off-by: Ran Wang
> ---
> drivers/Kconfig| 2 ++
> drivers/qe/Kconfig | 8
> 2 files changed, 10 insertions(+)
> create mode 100644 drivers/qe/Kconfig
>
> diff --git a/drivers/Kconfig b/driv
On 07/31/2018 11:15 PM, Peng Ma wrote:
> Add ahci compatible support for ls1021a soc.
>
> Signed-off-by: Peng Ma
> Acked-by: Michal Simek
> ---
> drivers/ata/sata_ceva.c | 24
> 1 files changed, 24 insertions(+), 0 deletions(-)
>
> writel(tmp, base + AH
On Thu, 2018-09-20 at 09:25 -0400, Thomas Epperson wrote:
> I've done some troubleshooting on warm resets and determined that the ocramis
> not being set correctly for warm reset to run properly (it hangs theprocessor
> on my de0-nano-soc board).I think it should be not enabled or fully setup so
>
On 09/20/2018 07:57 PM, Qiang Zhao wrote:
> Hi York,
>
> It seems nobody have comments on this patch,
> Could you help to take action on it?
>
I will try when I get a chance. Thanks.
York
___
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U-Boot@lists.denx.de
https://lists.denx
On 09/20/2018 11:50 PM, Heinrich Schuchardt wrote:
On 09/21/2018 12:55 AM, Stephen Warren wrote:
From: Stephen Warren
After a test has failed, test/py drains the U-Boot console log to ensure
that any relevant output is captured. At this point, we don't care about
detecting any additional error
On 08/21/2018 02:18 AM, Pramod Kumar wrote:
> ls1088ardb-pb is another varinat of the ls1088ardb.
> This board support two m.2 x2 gen 3 pcie card slot.
> There is no support of sata, pcie standard slot,
> miniPCIE slot and TDM in this board.
>
> Signed-off-by: Pramod Kumar
> ---
> Changes in v2:
On 09/21/2018 04:01 PM, Patrick DELAUNAY wrote:
> Hi Marek and Lucaz
>
> I have found this old patch: See
> https://lists.denx.de/pipermail/u-boot/2017-October/309716.html
>
> On 10/18/2017 10:22 PM, Marek Vasut-3 wrote:
>
>> On 10/18/2017 06:27 PM, Tom Rini wrote:
>>> On Wed, Oct 18, 2017 at
Hi Marek and Lucaz
I have found this old patch: See
https://lists.denx.de/pipermail/u-boot/2017-October/309716.html
On 10/18/2017 10:22 PM, Marek Vasut-3 wrote:
>On 10/18/2017 06:27 PM, Tom Rini wrote:
>> On Wed, Oct 18, 2017 at 04:03:21PM +0200, Patrick Delaunay wrote:
>>
>>> solve data ab
On Fri, Sep 21, 2018 at 1:43 PM Wolfgang Denk wrote:
>
> Dear Alex,
>
> In message <20180918081013.26660-1-alex.kier...@gmail.com> you wrote:
> > When the image which bootm is given can't be booted, call panic with
> > the error message rather than printf/hang so that we can recover from
> > broke
On 21/09/2018 12:43, Lukasz Majewski wrote:
Hi Jean-Jacques,
On 21/09/2018 11:24, Lukasz Majewski wrote:
Hi Jean-Jacques,
On 21/09/2018 10:50, Lukasz Majewski wrote:
Hi Jean-Jacques,
Hi Marek,
I haven't heard of you on this series.
It is already a resend and has been tested on
Dear Alex,
In message <20180918081013.26660-1-alex.kier...@gmail.com> you wrote:
> When the image which bootm is given can't be booted, call panic with
> the error message rather than printf/hang so that we can recover from
> broken images via a bootcount mechanism. If hang on failure is still
> r
Michal,
On 20/09/2018 at 08:23, Michal Simek wrote:
On 19.9.2018 20:08, Edgar E. Iglesias wrote:
On Wed, Sep 19, 2018 at 06:08:18PM +0200, Michal Simek wrote:
Clear ADDR64 dma bit in DMACFG register in case that HW_DMA_CAP_64B
is not detected on 64bit system.
The issue was observed when bootlo
>-Original Message-
>From: York Sun
>Sent: Wednesday, July 11, 2018 2:52 AM
>To: Pramod Kumar ; u-boot@lists.denx.de
>Subject: Re: [PATCH 1/2 v2] board: freescale: ls1012afrx:Common files to
>support
>
>On 06/06/2018 04:16 AM, Pramod Kumar wrote:
>> LS1012A-FRDM and LS1012A-FRWY board.
>>
- add neutis target to dtb makefile
- add dts file for Neutis N5
- add config file for Neutis N5
Signed-off-by: Aleksandr Aleksandrov
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/sun50i-h5-emlid-neutis-n5.dts | 90 ++
configs/emlid_neutis_n5_de
This set of patches introduce fastboot support for Qualcomm
db410c.
As part of the patch, a small quirk is added to ci_udc through
a weaklly linked function.
Changes in v2:
Added a new patch that was left out somehow. all other patches
are the same.
Ramon Fried (14):
ehci: Replace board_prepar
Fix sfp_verify_header to return correct version number.
This fixes "Not a sane SOCFPGA preloader" error message with v1 header.
Signed-off-by: Atsushi Nemoto
---
v2: move the *ver assignment to just before return.
tools/socfpgaimage.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/so
Hi Marek,
On Thu, 20 Sep 2018 15:31:05 +0200, Marek Vasut wrote:
> This *ver assignment should be just before return img_len, so we don't
> set the *ver until we did all the checks. Otherwise it's good. Can you
> send a V2 ?
Thank you for the review. I will post a new patch soon.
---
Atsushi N
I've done some troubleshooting on warm resets and determined that the ocram
is not being set correctly for warm reset to run properly (it hangs the
processor on my de0-nano-soc board).
I think it should be not enabled or fully setup so it properly works.
Hi Jean-Jacques,
> On 21/09/2018 11:24, Lukasz Majewski wrote:
> > Hi Jean-Jacques,
> >
> >> On 21/09/2018 10:50, Lukasz Majewski wrote:
> >>> Hi Jean-Jacques,
> >>>
> Hi Marek,
>
> I haven't heard of you on this series.
>
> It is already a resend and has been tes
Change ehci_usb_probe() function to initialize the
USB according to the init_type provided.
Signed-off-by: Ramon Fried
---
Changes in v2: None
drivers/usb/host/ehci-msm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/eh
Enable USB PHY driver.
Also fixed the alphabetically ordering of the config.
Signed-off-by: Ramon Fried
---
Changes in v2: None
configs/dragonboard410c_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/dragonboard410c_defconfig
b/configs/dragonboard410c_defconfig
index 96a
change writel to writebits32 in ci_pullup() in order
to keep phy configuration in tact.
Signed-off-by: Ramon Fried
---
Changes in v2:
Patch introduced
drivers/usb/gadget/ci_udc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gad
If during boot the key-vol-down press is detected
we'll fall back to fastboot.
Signed-off-by: Ramon Fried
---
Changes in v2: None
board/qualcomm/dragonboard410c/dragonboard410c.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/qualcomm/dragonboard410c/dragonboard410
MSM uses the chipidea controller IP, however it requires
to reinit the phy after controller reset. in EHCI mode there's a
dedicated callback for it.
In device mode however there's no such callback.
Add implementaion of ci_init_after_reset() to implement the above
requirement in case CI_UDC driver i
All the underlying USB PHY was handled in the ehci driver.
Use the generic phy API instead.
Signed-off-by: Ramon Fried
---
Changes in v2: None
drivers/usb/host/Kconfig| 3 +--
drivers/usb/host/ehci-msm.c | 52 +++--
2 files changed, 10 insertions(+), 45 del
MSM variant of Chipidea must reinitalize the phy
after controller reset.
Introduce ci_init_after_reset() weak function that
can be used to achieve the above init.
Signed-off-by: Ramon Fried
---
Changes in v2: None
drivers/usb/gadget/ci_udc.c | 6 ++
1 file changed, 6 insertions(+)
diff --
Signed-off-by: Ramon Fried
---
Changes in v2: None
configs/dragonboard410c_defconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/configs/dragonboard410c_defconfig
b/configs/dragonboard410c_defconfig
index 0d9008deb7..a55abaf8df 100644
--- a/configs/dragonboard410c_defconfig
Signed-off-by: Ramon Fried
---
Changes in v2: None
arch/arm/dts/dragonboard410c.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 75f28300b7..fa348bc621 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arc
The serial# environment variable needs to be
defined so it will be used by fastboot as serial
for the endpoint descriptor.
Signed-off-by: Ramon Fried
---
Changes in v2: None
arch/arm/mach-snapdragon/Kconfig | 1 +
board/qualcomm/dragonboard410c/dragonboard410c.c | 10 +
Add a PHY driver for the Qualcomm dragonboard 410c which
allows switching on/off and resetting the phy connected
to the EHCI controllers and USBHS controller.
Signed-off-by: Ramon Fried
---
Changes in v2: None
MAINTAINERS| 1 +
drivers/phy/Kconfig| 8 +++
dr
Alias is required so req-seq will be filled.
Signed-off-by: Ramon Fried
---
Changes in v2: None
arch/arm/dts/dragonboard410c.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index f4f7c350ec..75f28300b7 100644
--- a
platdata_auto_alloc_size was not initialized in structure.
Caused null pointer dereference when configuring device as
gadget.
Signed-off-by: Ramon Fried
---
Changes in v2: None
drivers/usb/host/ehci-msm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers
Use standard board_usb_init() instead of the specific board_prepare_usb.
Signed-off-by: Ramon Fried
---
Changes in v2: None
board/qualcomm/dragonboard410c/dragonboard410c.c | 4 ++--
drivers/usb/host/ehci-msm.c | 9 ++---
2 files changed, 4 insertions(+), 9 deletions(
On 21/09/2018 11:24, Lukasz Majewski wrote:
Hi Jean-Jacques,
On 21/09/2018 10:50, Lukasz Majewski wrote:
Hi Jean-Jacques,
Hi Marek,
I haven't heard of you on this series.
It is already a resend and has been tested on 2 platforms (zcu100
and dra7/am57).
Can you please consider it for i
Hi Jean-Jacques,
> On 21/09/2018 10:50, Lukasz Majewski wrote:
> > Hi Jean-Jacques,
> >
> >> Hi Marek,
> >>
> >> I haven't heard of you on this series.
> >>
> >> It is already a resend and has been tested on 2 platforms (zcu100
> >> and dra7/am57).
> >>
> >> Can you please consider it for inclus
On 09/21/2018 10:38 AM, Ley Foon Tan wrote:
> On Thu, Sep 20, 2018 at 6:20 PM Marek Vasut wrote:
>>
>> On 09/20/2018 06:22 PM, Ley Foon Tan wrote:
>>> Remove code from the reset manager that is never called.
>>>
>>> Signed-off-by: Ley Foon Tan
>>> ---
>>> .../mach-socfpga/include/mach/reset_mana
On 09/21/2018 11:08 AM, Bin Meng wrote:
> Hi Marek,
>
> On Thu, Sep 20, 2018 at 6:34 PM Marek Vasut wrote:
>>
>> On 09/20/2018 03:55 AM, Bin Meng wrote:
>>> Hi Marek,
>>>
>>> On Wed, Sep 19, 2018 at 9:29 PM Marek Vasut wrote:
On 09/18/2018 04:02 PM, Simon Glass wrote:
> Hi Marek,
>
> On 21.09.2018, at 10:59, Heiko Stuebner wrote:
>
> While trying to enable the dw_mmc on rk3188 I managed to confuse
> and hang the dw_mmc controller into not delivering further data.
> The fifo state never became ready and the driver was iterating in
> the while loop reading 0-byte packets for
> On 21.09.2018, at 10:59, Heiko Stuebner wrote:
>
> The rk3188 works nicely with the rockchip mmc driver, so we just need
> to add the different compatible for it - as used in the Linux kernel.
>
> Signed-off-by: Heiko Stuebner
Reviewed-by: Philipp Tomsich
Acked-by: Philipp Tomsich
_
On 21.09.2018, at 10:59, Heiko Stuebner wrote:
>
> The dwmmc controllers on rk3188 do not have idma support, so need to
> use the fifo-mode and it my tests they became confused and stopped
> working if the frequency was to high.
>
> While I only tested in somewhat bigger steps, 32MHz for example
> On 21.09.2018, at 10:59, Heiko Stuebner wrote:
>
> It is good practice to make the setting of gpio-pinctrls explicitly in the
> devicetree, and in this case even necessary.
> Rockchip boards start with iomux settings set to gpio for most pins and
> while the linux pinctrl driver also implicit
Hi Trevor,
Am Mittwoch, 2. Mai 2018, 09:10:49 CEST schrieb Kever Yang:
> Hi Trevor,
>
> It looks like the mmc driver does not work correctly, and no
> emmc/sdcard found.
I just sent off a series adding mmc support for rk3188 in u-boot, so
maybe you could try that.
Heiko
_
Hi Marek,
On Thu, Sep 20, 2018 at 6:34 PM Marek Vasut wrote:
>
> On 09/20/2018 03:55 AM, Bin Meng wrote:
> > Hi Marek,
> >
> > On Wed, Sep 19, 2018 at 9:29 PM Marek Vasut wrote:
> >>
> >> On 09/18/2018 04:02 PM, Simon Glass wrote:
> >>> Hi Marek,
> >>
> >> Hi,
> >>
> >>> On 18 September 2018 at
The dwmmc controllers on rk3188 do not have idma support, so need to
use the fifo-mode and it my tests they became confused and stopped
working if the frequency was to high.
While I only tested in somewhat bigger steps, 32MHz for example
hung the controller, while reducing it to 16MHz worked just
It is good practice to make the setting of gpio-pinctrls explicitly in the
devicetree, and in this case even necessary.
Rockchip boards start with iomux settings set to gpio for most pins and
while the linux pinctrl driver also implicitly sets the gpio function if
a pin is requested as gpio that is
The rk3188 works nicely with the rockchip mmc driver, so we just need
to add the different compatible for it - as used in the Linux kernel.
Signed-off-by: Heiko Stuebner
---
drivers/mmc/rockchip_dw_mmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/
While trying to enable the dw_mmc on rk3188 I managed to confuse
and hang the dw_mmc controller into not delivering further data.
The fifo state never became ready and the driver was iterating in
the while loop reading 0-byte packets forever.
So inspired by how other implementations handle this, c
With this series I can now sucessfully boot from a sd-card, with
even big kernels being read sucessfully.
Patch 1 is not strictly necessary for that but was a result of me
investigating the mmc hang which even hung the whole uboot.
Heiko Stuebner (4):
mmc: dw_mmc: check fifo status with a timeo
On 21/09/2018 10:50, Lukasz Majewski wrote:
Hi Jean-Jacques,
Hi Marek,
I haven't heard of you on this series.
It is already a resend and has been tested on 2 platforms (zcu100 and
dra7/am57).
Can you please consider it for inclusion?
This is not Marek to blame for the delay - I had some n
Hi Jean-Jacques,
> Hi Marek,
>
> I haven't heard of you on this series.
>
> It is already a resend and has been tested on 2 platforms (zcu100 and
> dra7/am57).
>
> Can you please consider it for inclusion?
This is not Marek to blame for the delay - I had some non open source
tasks to finish (
On Thu, Sep 20, 2018 at 6:20 PM Marek Vasut wrote:
>
> On 09/20/2018 06:22 PM, Ley Foon Tan wrote:
> > Remove code from the reset manager that is never called.
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > .../mach-socfpga/include/mach/reset_manager_s10.h | 2 --
> > arch/arm/mach-socfpga/re
Hi Marek,
I haven't heard of you on this series.
It is already a resend and has been tested on 2 platforms (zcu100 and
dra7/am57).
Can you please consider it for inclusion?
Thanks,
JJ
On 04/09/2018 15:42, Jean-Jacques Hiblot wrote:
Resending this series after rebasing on top of latest u
Hi Jagan,
Jagan Teki wrote on Fri, 21 Sep 2018
13:45:56 +0530:
> On Thu, Sep 20, 2018 at 8:29 PM Miquel Raynal
> wrote:
> >
> > Hi Jagan, Frieder,
> >
> > Jagan Teki wrote on Thu, 20 Sep 2018
> > 20:16:06 +0530:
> >
> > > On Thu, Sep 20, 2018 at 7:36 PM, Frieder Schrempf
> > > wrote:
> >
On Thu, Sep 20, 2018 at 8:29 PM Miquel Raynal wrote:
>
> Hi Jagan, Frieder,
>
> Jagan Teki wrote on Thu, 20 Sep 2018
> 20:16:06 +0530:
>
> > On Thu, Sep 20, 2018 at 7:36 PM, Frieder Schrempf
> > wrote:
> > > Hi Jagan,
> > >
> > > I just wanted to ask about the timeline for the SPI-NAND patches.
Makefile entries should be sorted.
Reviewed-by: Anatolij Gustschin
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
Signed-off-by: Anatolij Gustschin
---
v6 -> v7:
No changes
v5 -> v6:
No changes
v4 -> v5:
Drop re-ordered entries that are not in mainline
(e.g. CONFIG_GDSYS_IOEP, CONFIG_MP
Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which
supports initialization of the FPGA, as well as information gathering.
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
---
v6 -> v7:
No changes
v5 -> v6:
No changes
v4 -> v5:
No changes
v3 -> v4:
* Switched from 'res' a
Add some debug output in cases where the initialization of a regmap
fails.
Reviewed-by: Anatolij Gustschin
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
---
v6 -> v7:
No changes
v5 -> v6:
No changes
v4 -> v5:
No changes
v3 -> v4:
No changes
v2 -> v3:
New in v3
---
drivers/core/regma
This patch adds a driver for the bus associated with a IHS FPGA.
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
---
v6 -> v7:
No changes
v5 -> v6:
No changes
v4 -> v5:
No changes
v3 -> v4:
No changes
v2 -> v3:
* Fixed style violations
* Added bindings file
* Added more debug output in c
Both fdtdec_get_addr_size_fixed and of_address_to_resource can fail with
an error, which is not currently checked during regmap initialization.
Since the indentation depth is already quite deep, extract a new
'init_range' method to do the initialization.
Reviewed-by: Anatolij Gustschin
Reviewed-
It is useful to be able to treat the different ranges of a regmap
separately to be able to use distinct offset for them, but this is
currently not implemented in the regmap API.
To preserve backwards compatibility, add regmap_read_range and
regmap_write_range functions that take an additional para
It would be convenient if one could use the regmap API in conjunction
with register maps defined as structs (i.e. structs that directly mirror
the memory layout of the registers in question). A similar approach was
planned with the regmap_write32/regmap_read32 macros, but was never
used.
Hence, im
The regmap functions currently assume that all register map accesses
have a data width of 32 bits, but there are maps that have different
widths.
To rectify this, implement the regmap_raw_read and regmap_raw_write
functions from the Linux kernel API that specify the width of a desired
read or writ
Add test for regmap_{set,get} functions.
Reviewed-by: Anatolij Gustschin
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
---
v6 -> v7:
No changes
v5 -> v6:
No changes
v4 -> v5:
No changes
v3 -> v4:
No changes
v2 -> v3:
New in v3
---
test/dm/regmap.c | 28
The documentation in regmap.h is not in kernel-doc format. Correct this.
Reviewed-by: Anatolij Gustschin
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
---
v6 -> v7:
No changes
v5 -> v6:
No changes
v4 -> v5:
No changes
v3 -> v4:
No changes
v2 -> v3:
New in v3
---
include/regmap.h | 4
ofnode_read_simple_addr_cells may fail and return a negative error code.
Check for this when initializing regmaps.
Also check if both_len is zero, since this is perfectly possible, and
would lead to a division-by-zero further down the line.
Reviewed-by: Anatolij Gustschin
Reviewed-by: Simon Glas
Document the regmap_alloc() function.
Reviewed-by: Anatolij Gustschin
Reviewed-by: Simon Glass
Signed-off-by: Mario Six
---
v6 -> v7:
No changes
v5 -> v6:
No changes
v4 -> v5:
No changes
v3 -> v4:
No changes
v2 -> v3:
New in v3
---
drivers/core/regmap.c | 6 ++
1 file changed, 6 ins
The upcoming changes to the regmap interface will contain a proper check
for plausibility when reading/writing from/to a register map. To still
have the current tests pass, increase the size of the memory region for
the syscon0 device, since one of the tests reads and writes beyond this
range.
Rev
MIPS is the only architecture currently supported by U-Boot that does
not implement any of the in/out register access functions.
To have a interface that is useable across architectures, add the
functions to the MIPS architecture (implemented using the __raw_write
and __raw_read functions).
Signe
Hi Simon,
On Fri, Aug 17, 2018 at 2:52 PM Simon Glass wrote:
>
> Hi Mario,
>
> On 13 August 2018 at 00:09, Mario Six wrote:
> > The regmap functions currently assume that all register map accesses
> > have a data width of 32 bits, but there are maps that have different
> > widths.
> >
> > To rec
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