Hi Tom
On 03/09/2017 08:09 PM, Tom Rini wrote:
> On Mon, Mar 06, 2017 at 09:45:09AM +, Patrice CHOTARD wrote:
>> Hi Tom
>>
>> As kernel maintainer of STi machine (STMicroelectronics STiH407 family
>> SoC), i am currently adding STiH407 support on U-boot
>> (https://www.mail-archive.com/u-boot@
On 03/10/2017 05:05 AM, Kever Yang wrote:
> Some board do not use the dwc2 internal VBUS_DRV signal, but
> use a gpio pin to enable the 5.0V VBUS power, add interface to
> enable the power in dwc2 driver.
>
> Signed-off-by: Kever Yang
> Signed-off-by: Simon Glass
Applied, thanks.
--
Best rega
On 03/10/2017 05:02 AM, Kever Yang wrote:
> Hi Marek,
>
> On 03/10/2017 10:16 AM, Marek Vasut wrote:
>> On 03/07/2017 07:50 AM, Kever Yang wrote:
>>> Hi Marek,
>>>
>>> On 03/07/2017 10:55 AM, Marek Vasut wrote:
On 03/06/2017 01:54 PM, Kever Yang wrote:
> Some board do not use the dwc2 in
On Thu, 9 Mar 2017 21:55:44 -0600
James Balean wrote:
> This patch adds a pin controller driver supporting devices using a
> single configuration register per pin.
>
> Signed-off-by: Felix Brack
> [ja...@balean.com.au: changed .set_state_simple operation
> to .set_state] Signed-off-by: James B
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang
Signed-off-by: Simon Glass
---
Changes in v5:
- add ifdef around the function instead of inside the function.
C
Hi Marek,
On 03/10/2017 10:16 AM, Marek Vasut wrote:
On 03/07/2017 07:50 AM, Kever Yang wrote:
Hi Marek,
On 03/07/2017 10:55 AM, Marek Vasut wrote:
On 03/06/2017 01:54 PM, Kever Yang wrote:
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS p
This patch adds a pin controller driver supporting devices using a single
configuration register per pin.
Signed-off-by: Felix Brack
[ja...@balean.com.au: changed .set_state_simple operation to .set_state]
Signed-off-by: James Balean
---
drivers/pinctrl/Kconfig | 10 +++
drivers/pinc
Hi Jernej,
在 2017年03月09日 07:34, Jernej Skrabec 写道:
Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.
DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.
EDID reading code
On 03/07/2017 07:50 AM, Kever Yang wrote:
> Hi Marek,
>
> On 03/07/2017 10:55 AM, Marek Vasut wrote:
>> On 03/06/2017 01:54 PM, Kever Yang wrote:
>>> Some board do not use the dwc2 internal VBUS_DRV signal, but
>>> use a gpio pin to enable the 5.0V VBUS power, add interface to
>>> enable the powe
On 03/07/2017 10:47 PM, Stephen Arnold wrote:
Where is 2/2 patch ?
The commit message should say "socfpga: Update README with handoff
generation instructions", the rest is just fluff . And btw. those
instructions came from my internal notes ;-)
> From v2-U-Boot-arm-socfpga-Add-SoCFPGA-SR1500-boa
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add config and defconfig for the Arria10 and update socfpga_common.h.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> configs/socfpga_arria10_defconfig | 30 +++
> include/configs/socfpga_arria10_socdk.h | 6
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add misc support for Arria 10 and minor fix on misc Gen5.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/Makefile| 1 +
> arch/arm/mach-socfpga/include/mach/misc.h | 6 +
> arch/arm/mach
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add SPL support for Arria 10 and add reset_uart() to use in SPL.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> .../include/mach/reset_manager_arria10.h | 1 +
> arch/arm/mach-socfpga/reset_manager_arria10.c
On 03/07/2017 04:18 PM, Rush, Jason A. wrote:
> Marek Vasut wrote:
>> On 03/03/2017 04:17 PM, Rush, Jason A. wrote:
>>> Marek Vasut wrote:
On 03/01/2017 05:36 PM, Rush, Jason A. wrote:
> This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.
>
> The Cadence QSPI device does
On 03/09/2017 10:32 PM, Dinh Nguyen wrote:
> On Wed, Mar 8, 2017 at 6:26 PM, Ley Foon Tan wrote:
>> This is the 2nd version of patchset to adds support for Intel Arria 10 SoC.
>> This version mainly resolved comments from Marek in [v1].
>>
>
> Can you please include me on this patchset? I'd like
On 03/07/2017 05:45 PM, york sun wrote:
> On 03/06/2017 10:36 PM, Marek Vasut wrote:
>> On 03/07/2017 05:31 AM, york sun wrote:
>>> On 03/06/2017 07:59 PM, Marek Vasut wrote:
On 03/06/2017 06:02 PM, York Sun wrote:
> Early MMU improves performance especially on emulators. However, the
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Convert Altera ddr driver to use Kconfig method. Enable ALTERA_SDRAM
> by default if it is on Gen5 target. Arria 10 will have different driver.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> drivers/Kconfig
On 03/07/2017 03:41 PM, Gary Bisson wrote:
> Hi Marek, All,
>
> On Tue, Mar 07, 2017 at 03:52:23AM +0100, Marek Vasut wrote:
>> On 03/06/2017 11:21 PM, Steve Rae wrote:
>>> The "chunks" in the "fastboot sparse image" are not aligned,
>>> resulting in many "cached misaligned" messages from
>>> chec
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> These registers only available for Gen5 device, excludes them
exclude
> if for Arria 10 build.
s/if for/from/
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> drivers/fpga/socfpga.c | 6 ++
> 1 file changed, 6 insertions(
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add pinmux support for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/Makefile | 1 +
> arch/arm/mach-socfpga/include/mach/pinmux.h | 15 +
> arch/arm/mach-socfpga/pinmux_arr
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add clock driver support for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/Makefile |3 +-
> arch/arm/mach-socfpga/clock_manager.c | 18 +-
> arch/arm/m
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add system manager register struct and defines for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> .../arm/mach-socfpga/include/mach/system_manager.h | 52 ++
> .../include/mach/system_manager_arria10.h
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add reset driver support for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
> .../include/ma
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add i2c, timer and other A10 defines.
macros ... btw. you're defining macro with their address.
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Restructure misc driver in the preparation to support A10.
> Move the Gen5 specific code to _gen5 file. No functional change.
>
> Change all uint32_t_to u32.
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/Makefile| 3 +-
On 03/09/2017 10:55 PM, Vikas Manocha wrote:
> This patch adds armv7m instruction & data cache support.
>
> Signed-off-by: Vikas Manocha
> ---
> arch/arm/cpu/armv7m/Makefile | 2 +-
> arch/arm/cpu/armv7m/cache.c | 295
> ++
> arch/arm/include/asm/arm
On 03/06/2017 09:03 AM, York Sun wrote:
> A recent debug revealed MMU for DDR shouldn't be enabled before
> DDR is initialized. Otherwise, a "normal memory" mapping may cause
> speculative access which may hang the system if accessing to DDR
> is not allowed at time. For Layerscape platforms, we h
This series implements support for HDMI output. This is done using
DM video framework and sharing the HDMI controller code with RK3288.
First and second patch fix audio clock issue and remove unneeded CSC
initialization in RK3288 HDMI driver. I think audio initialization is
also not really needed,
From: Stefan Agner
Use two separate partitions for the two firmware instances. Also
resize them to be of the same size which also makes the start of
the UBI partition nicely aligned to 0x40.
In order to detect the new MTD layout and whether we run a U-Boot
with the new BCB format or not, int
From: Stefan Agner
Use device-tree fixup to communicate the MTD partitions to the
kernel. Remove mtdparts from the kernel command line.
Signed-off-by: Stefan Agner
---
board/toradex/colibri_imx7/colibri_imx7.c | 13 +
configs/colibri_imx7_defconfig| 1 +
include/confi
From: Stefan Agner
Implement board level USB PHY mode callback. On USB OTG Port 1
the Colibri standard foresees GPIO USBC_DET to decide whether the
port should run in Host or Device mode.
Signed-off-by: Stefan Agner
---
board/toradex/colibri_imx7/colibri_imx7.c | 28 ++
From: Stefan Agner
Disable 3.3V Ethernet and ARM rail when entering sleep mode.
Signed-off-by: Stefan Agner
---
board/toradex/colibri_imx7/colibri_imx7.c | 16
1 file changed, 16 insertions(+)
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c
b/board/toradex/colibri_im
From: Stefan Agner
Device tree overlays might prove useful in the future, enable it
by default on all Toradex modules.
Signed-off-by: Stefan Agner
Acked-by: Max Krummenacher
---
configs/apalis_imx6_defconfig | 1 +
configs/apalis_t30_defconfig | 1 +
configs/colibri_imx6_defconfig | 1 +
From: Stefan Agner
Limit memory used for relocation of FDT or initrd. This is
required to make sure that relocated artifacts are within lowmem.
If fdt_high or initrd_high are not set, U-Boot automatically
relocates artifacts to the end of memory. But this area won't
be part of lowmem and hence wi
From: Stefan Agner
All modules use the common g_dnl_bind_fixup implementaton which
calculates the PID according to product id (read from the config
block) plus offset of 0x4000. In case there is no config block
support (e.g. SPL) or in case the config block is not readable,
fall back to a generic
From: Stefan Agner
The first two patches are common to all our modules, the next is
touching all our NXP based modules and the rest of the patches are
Colibri iMX7 related. Since all patches touch defconfig splitting
them would lead to merge issues, so I kept them in a single patch
set. Can this
It also enables commands for cache enable/disable/status.
Signed-off-by: Vikas Manocha
---
arch/arm/mach-stm32/stm32f7/soc.c | 2 ++
include/configs/stm32f746-disco.h | 4 +---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-stm32/stm32f7/soc.c
b/arch/arm/mach-stm32
This patch adds armv7m instruction & data cache support.
Signed-off-by: Vikas Manocha
---
arch/arm/cpu/armv7m/Makefile | 2 +-
arch/arm/cpu/armv7m/cache.c | 295 ++
arch/arm/include/asm/armv7m.h | 23 +++-
arch/arm/lib/Makefile | 2 +
4 fil
This patchset adds armv7m instruction/data caches support &
enable it for stm32f7.
Vikas Manocha (2):
armv7m: add instruction & data cache support
stm32f7: enable instruction & data cache
arch/arm/cpu/armv7m/Makefile | 2 +-
arch/arm/cpu/armv7m/cache.c | 295
Tom,
The following changes since commit 0574f786d3c85ab1a9fe9ee8ade65e3ae83e18a4:
Merge branch 'master' of git://git.denx.de/u-boot-video (2017-03-08
07:14:21 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git
for you to fetch changes up to bbf04d4e809
On Wed, Mar 8, 2017 at 6:26 PM, Ley Foon Tan wrote:
> This is the 2nd version of patchset to adds support for Intel Arria 10 SoC.
> This version mainly resolved comments from Marek in [v1].
>
Can you please include me on this patchset? I'd like to help with the
review process.
Thanks,
Dinh
_
On 01/31/2017 11:01 PM, Vinitha Pillai-B57223 wrote:
> From: Vinitha Pillai
>
> Raw uboot image is used in place of FIT image in secure boot.
> The maximum allocated size of raw u-boot bin is 1MB in memory map.
> Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB.
> The bootscript (BS_ADDR)
On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> Priyanka Jain (3):
> armv8: fsl-layerscape: Updates DCFG register map.
> armv8: fsl-lsch3: Update VID support
> armv8: fsl-layerscape: Add vid support for LS2080AQDS.
>
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 69 ++---
> boa
On 02/05/2017 07:42 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Remove the DDR interactive debugging to reduce the size of spl image.
>
> Signed-off-by: Hou Zhiqiang
> ---
> include/configs/ls1043aqds.h | 2 ++
> include/configs/ls1043ardb.h | 2 ++
> include/configs/ls1046aqds.h | 2 ++
>
On 02/06/2017 10:32 PM, yuantian.t...@nxp.com wrote:
> From: Tang Yuantian
>
> Read DMA operations causes CRC error on armv8 chassis 2 platforms
> due to the erratum A-010635.
> In order to support sata on these platforms, ECC needs to be disabled.
>
> Signed-off-by: Tang Yuantian
> ---
> v2:
>
On Thu, 9 Mar 2017 08:08:20 -0500
Tom Rini wrote:
> On Thu, Mar 02, 2017 at 01:04:16PM -0600, Franklin S Cooper Jr wrote:
>
> > Runtime U-boot dtb selection is generally a two step process. First
> > step is to simply use an initial generic dtb. The second step is to
> > select the dtb and perha
On Mon, Mar 06, 2017 at 09:45:09AM +, Patrice CHOTARD wrote:
> Hi Tom
>
> As kernel maintainer of STi machine (STMicroelectronics STiH407 family
> SoC), i am currently adding STiH407 support on U-boot
> (https://www.mail-archive.com/u-boot@lists.denx.de/msg239825.html).
>
> I am wondering if
On Tue, Mar 07, 2017 at 11:20:08AM -0500, Tom Rini wrote:
> Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support
> using hardware acceleration.") created entries for CONFIG_SHA1,
> CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
> However, no defconfig has migrated t
We rename CONFIG_FIT_DISABLE_SHA256 to CONFIG_FIT_ENABLE_SHA256_SUPPORT which
is enabled by default and now a positive option. Convert the handful of boards
that were disabling it before to save space.
Cc: Dirk Eibach
Cc: Lukasz Dalek
Signed-off-by: Tom Rini
Reviewed-by: Simon Glass
---
Chang
Hi Maxime,
Dne četrtek, 09. marec 2017 ob 09:33:06 CET je Maxime Ripard napisal(a):
> Hi,
>
> Thanks for your great work.
>
> On Thu, Mar 09, 2017 at 12:34:40AM +0100, Jernej Skrabec wrote:
> > - writel(0, &lcdc->tcon0_io_tristate);
> > + sunxi_ctfb_mode_to_display_timing(mode, &timing);
> >
Hi Tom,
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Thursday, March 09, 2017 8:18 AM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v3 00/10] stm32f7: add clock and pin control
> drivers
>
> On Thu, Mar 09, 2017 at 03:36:29PM
On 03/08/2017 06:26 PM, Ley Foon Tan wrote:
> Rename some of variables and fixes on clock calculation.
>
Why? Please be more specific with why this change is necessary?
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/mach-socfpga/clock_manager_gen5.c | 126
>
On 03/08/2017 06:26 PM, Ley Foon Tan wrote:
> Restructure clock manager driver in the preparation to support A10.
> Move the Gen5 specific code to _gen5 files. No functional change.
>
> Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
>
> Signed-off-by: Ley Foon Tan
> -
On Thu, Mar 09, 2017 at 03:36:29PM +, Vikas MANOCHA wrote:
> Thanks Tom,
>
> > -Original Message-
> > From: Tom Rini [mailto:tr...@konsulko.com]
> > Sent: Wednesday, March 01, 2017 7:39 AM
> > To: Vikas MANOCHA
> > Cc: u-boot@lists.denx.de
> > Subject: Re: [PATCH v3 00/10] stm32f7: ad
Thanks Tom,
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Wednesday, March 01, 2017 7:39 AM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH v3 00/10] stm32f7: add clock and pin control drivers
>
> On Mon, Feb 27, 2017 at 05:33:58PM +,
On Thu, Mar 02, 2017 at 01:04:35PM -0600, Franklin S Cooper Jr wrote:
> Include K2G ICE to OF_LIST so it can be used for runtime board
> detection.
>
> Signed-off-by: Franklin S Cooper Jr
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital signature
On Thu, Mar 02, 2017 at 01:04:34PM -0600, Franklin S Cooper Jr wrote:
> K2G ICE evm will have its own dtb. Therefore, add it to the list of dtbs
> located in the appended U-boot dtb FIT image. Therefore, when swapping out
> dtbs K2G ICE boards can grab the correct one.
>
> Signed-off-by: Franklin
On Thu, Mar 02, 2017 at 01:04:32PM -0600, Franklin S Cooper Jr wrote:
> Disable netcp by default like all other peripherals in the dtsi file.
> Enable the peripheral explicitly in the board specific dts file.
>
> Signed-off-by: Franklin S Cooper Jr
Has this been pushed up to Linux yet? Thanks!
On Thu, Mar 02, 2017 at 01:04:22PM -0600, Franklin S Cooper Jr wrote:
> Enable various config options to allow U-boot at runtime to select the
> proper dtb to use from the list of dtb's within the FIT image.
>
> Signed-off-by: Franklin S Cooper Jr
... but is the goal here to eventually support
On Thu, Mar 02, 2017 at 01:04:33PM -0600, Franklin S Cooper Jr wrote:
> Add basic DT support for K2G ICE evm. Only minimal peripherals are
> supported to allow console output and MMC boot.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> arch/arm/dts/Makefile | 3 ++-
> arch/arm/dts
On Thu, Mar 02, 2017 at 01:04:29PM -0600, Franklin S Cooper Jr wrote:
> Some code doesn't apply to K2G ICE evm. Therefore, use board detection to
> wrap these calls.
>
> Signed-off-by: Franklin S Cooper Jr
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital signature
__
On Thu, Mar 02, 2017 at 01:04:23PM -0600, Franklin S Cooper Jr wrote:
> Future boards will need to configure DDR3 registers in a slightly
> different manner. Support this by defining additional variables and
> defines that will be utilized later.
>
> Signed-off-by: Franklin S Cooper Jr
Reviewed
On Thu, Mar 02, 2017 at 01:04:18PM -0600, Franklin S Cooper Jr wrote:
> u-boot.bin is a copy of:
> u-boot-fit-dtb.bin if CONFIG_FIT_EMBED is enabled,
> u-boot-dtb.bin if CONFIG_OF_SEPARATE is enabled,
> u-boot-nodtb.bin if DT is not enabled.
> So, use u-boot.bin to to generate keystone images inst
On Thu, Mar 02, 2017 at 01:04:13PM -0600, Franklin S Cooper Jr wrote:
> Scratch space can be used for features such as board detection. Define
> an area within SRAM that can be used for this purpose.
>
> Signed-off-by: Franklin S Cooper Jr
> Signed-off-by: Roger Quadros
> ---
> include/configs/
On Thu, Mar 02, 2017 at 01:04:24PM -0600, Franklin S Cooper Jr wrote:
> K2G GP doesn't require the MR2 register to be programed since the
> default is good enough. However, newer K2G boards do need to change
> this register value. Therefore, instead of not writing this register if
> ran on a K2G b
On Thu, Mar 02, 2017 at 01:04:28PM -0600, Franklin S Cooper Jr wrote:
> Add configuration settings used by the K2G ICE evm. Also use board
> detection to determine which DDR3 configuration to use.
>
> Signed-off-by: Franklin S Cooper Jr
Reviewed-by: Tom Rini
--
Tom
signature.asc
Descriptio
On Thu, Mar 02, 2017 at 01:04:19PM -0600, Franklin S Cooper Jr wrote:
> For K2G, runtime DTB selection utilitizes the embedded_dtb_select function.
> Therefore, define the function which will perform a EEPROM read and then
> retries selecting the correct dtb now that it can detect which board its
On Thu, Mar 02, 2017 at 01:04:20PM -0600, Franklin S Cooper Jr wrote:
> Now with support for U-boot runtime dtb selection each board needs to
> define board_fit_config_name_match so U-boot can determine what the
> correct dtb is within the FIT blob.
>
> Signed-off-by: Franklin S Cooper Jr
Revie
On Thu, Mar 02, 2017 at 01:04:31PM -0600, Franklin S Cooper Jr wrote:
> Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG to allow "board_name" to
> be set depending on the board it is being ran on.
>
> Update findfdt to use this new dynamic board_name value to determine
> which dtb should be used.
>
On Thu, Mar 02, 2017 at 01:04:21PM -0600, Franklin S Cooper Jr wrote:
> Some K2G evms have their EEPROM programming while most do not. Therefore,
> add EEPROM board detection to be used as the default method and fall back
> to the alternative board detection when needed.
>
> Also reorder board co
On Thu, Mar 02, 2017 at 01:04:16PM -0600, Franklin S Cooper Jr wrote:
> Runtime U-boot dtb selection is generally a two step process. First step
> is to simply use an initial generic dtb. The second step is to select
> the dtb and perhaps execute additional code ones U-boot knows what board
> it i
On Thu, Mar 02, 2017 at 01:04:25PM -0600, Franklin S Cooper Jr wrote:
> Different K2G evms may need to program the various
> KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use
> the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to
> properly program the register.
>
On Thu, Mar 02, 2017 at 01:04:08PM -0600, Franklin S Cooper Jr wrote:
> This patch gives U-boot the runtime support to have the board specific
> code decide which FDT to use. This is especially useful for devices
> that need this type of runtime determination and also doesn't use SPL.
>
> Signed-
On Thu, Mar 02, 2017 at 01:04:15PM -0600, Franklin S Cooper Jr wrote:
> K2G boards have a EEPROM that will be used for board detection. Therefore,
> select the board detection config for K2G evms.
>
> Signed-off-by: Franklin S Cooper Jr
Reviewed-by: Tom Rini
--
Tom
signature.asc
Descriptio
On Thu, Mar 02, 2017 at 01:04:26PM -0600, Franklin S Cooper Jr wrote:
> Add a function that can be used to determine if the board being ran on is
> a K2G Industrial Communication Engine EVM or K2G General Purpose EVM based
> on values programmed on the EEPROM.
>
> Signed-off-by: Franklin S Cooper
On Thu, Mar 02, 2017 at 01:04:30PM -0600, Franklin S Cooper Jr wrote:
> Certain peripherals used by K2G GP aren't used on K2G ICE evm. Or
> configuration is slightly different. Therefore, use board detection to
> deal with these variations.
>
> Signed-off-by: Franklin S Cooper Jr
Reviewed-by: T
On Thu, Mar 02, 2017 at 01:04:27PM -0600, Franklin S Cooper Jr wrote:
> Add basic pinmux data for new K2G ICE evm. Also add pinmuxing for a
> generic K2G evm which includes I2C 0 and 1 used for board detection
> purposes.
>
> Since multiple K2G boards are supported that means initially generic
>
On Thu, Mar 02, 2017 at 01:04:17PM -0600, Franklin S Cooper Jr wrote:
> Add additional make targets and options for building embedded FIT U-boot
> images.
>
> Signed-off-by: Franklin S Cooper Jr
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital signature
_
On Thu, Mar 02, 2017 at 01:04:09PM -0600, Franklin S Cooper Jr wrote:
> When the EEPROM is first read its contents are stored in memory as a
> cache to avoid further I2C operations. To determine if the EEPROM was
> previously read the easiest way is to check the memory to see if the
> EEPROM's mag
On Tue, Mar 07, 2017 at 09:27:52PM -0600, Adam Ford wrote:
> A previous patch broke the board. This patch will add missing part
> from the previous patch and also move the SPL Stack into SDRAM at
> 0x8200.
>
> Tested with GCC 4.8.2 and GCC 6.2
>
> Fixes: 0959649dc6d9 ("omap3_logic: Switch to
On Tue, Mar 07, 2017 at 09:25:53PM +0100, Anatolij Gustschin wrote:
> Hi Tom,
>
> The following changes since commit 3fd2b3aa19b9479b5e785087e4951d3a7bbb87be:
>
> net: macb: Fix ETH not found when clock not support (2017-03-01 21:28:39
> -0500)
>
> are available in the git repository at:
>
On Wed, Mar 08, 2017 at 11:36:06PM -0500, Trevor Woerner wrote:
> On Wed 2017-03-08 @ 06:17:13 PM, Tom Rini wrote:
> > On Wed, Mar 08, 2017 at 05:32:45PM -0500, Trevor Woerner wrote:
> > > On Wed 2017-03-08 @ 04:33:21 PM, Tom Rini wrote:
> > > > Now, you've boot tested this, right? :)
> > >
> > >
Hi Jaehoon,
Thanks a lot for your comments!
> -Original Message-
> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Sent: 2017年3月8日 19:06
> To: Z.Q. Hou ; u-boot@lists.denx.de;
> o...@buserror.net; york sun ; mingkai...@freescale.com;
> s...@chromium.org; Xiaobo Xie
> Subject: Re: [
On Mon, Mar 06, 2017 at 10:48:15AM -0500, Tom Rini wrote:
> On Mon, Mar 06, 2017 at 03:11:29PM +, Andre Przywara wrote:
> > Hi,
> >
> > On 06/03/17 10:00, Maxime Ripard wrote:
> > > On Fri, Mar 03, 2017 at 09:55:25AM +, Andre Przywara wrote:
> > >> Hi,
> > >>
> > >> On 03/03/17 09:22, Maxi
On Wed, 2017-03-08 at 22:38 +0800, Eddie Cai wrote:
> 2017-03-08 17:29 GMT+08:00 Sjoerd Simons uk>:
>
> > On Wed, 2017-03-08 at 09:30 +0800, Eddie Cai wrote:
> > > Hi Simon
> > >
> > > 2017-03-06 14:46 GMT+08:00 Eddie Cai :
> > >
> > > > Hi Simon
> > > >
> > > > 2017-02-23 11:33 GMT+08:00 Simo
On Wednesday 08 March 2017 08:11 PM, Tom Rini wrote:
> On Mon, Mar 06, 2017 at 03:16:57PM +0530, Vignesh R wrote:
>> Hi,
>>
>> On Saturday 04 March 2017 10:39 PM, Tom Rini wrote:
>>> On Sat, Mar 04, 2017 at 06:17:30PM +0530, Vignesh R wrote:
>>>
SPI U-Boot image for K2 boards have now exceed
Hi,
Thanks for your great work.
On Thu, Mar 09, 2017 at 12:34:40AM +0100, Jernej Skrabec wrote:
> - writel(0, &lcdc->tcon0_io_tristate);
> + sunxi_ctfb_mode_to_display_timing(mode, &timing);
> + lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
> + s
87 matches
Mail list logo
