Hi Simon,
On 05-02-15 04:34, Simon Glass wrote:
Hi Jeroen,
On 4 February 2015 at 12:37, Jeroen Hofstee wrote:
Hello Guilherme / Simon,
It seems that commit f86ed6a8d52c99bb2d17d3cac1647edca0c4399c,
"tools: moved code common to all image tools to a separated module."
cause some trouble when
Hi,
On 02/05/2015 04:07 AM, Simon Glass wrote:
> Hi Michal,
>
> On 3 February 2015 at 17:40, Simon Glass wrote:
>> Hi Michal,
>>
>> On 3 February 2015 at 02:11, Michal Simek wrote:
>>> Hi Simon,
>>>
>>> On 02/03/2015 03:02 AM, Masahiro Yamada wrote:
Hi.
On Mon, 2 Feb 2015 16
Hi Simon,
On Thu, Feb 5, 2015 at 6:35 AM, Bin Meng wrote:
> Hi Simon,
>
> On Thu, Feb 5, 2015 at 12:25 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 3 February 2015 at 04:45, Bin Meng wrote:
>>> Turn on the Memory Reference code build in the quark Makefile.
>>>
>>> Signed-off-by: Bin Meng
>>> ---
Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), checkboard() is invoked only when
show_board_info() fails to get the model name from Device Tree.
It never happens because UniPhier SoCs now only work with
CONFIG_OF_CONTROL and all the root nodes of UniPhier device t
This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.
The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv7/uniphier/Makefile
To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0)
and bit 11 (SCL1/SDA1) of IECTRL register must be set.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/p
It is true that unused functions are removed from the ELF image
by the compiler's garbage collection but relying on it too much
does not look nice.
Currently, the build is taking more than it should.
Refactor the makefiles to compile only files that are really needed.
CONFIG_SOC_INIT and CONFIG_DR
Currently, I/O pin settings are not necessary for SPL.
The board_early_init_f() seems a suitable place to call pin_init().
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv7/uniphier/Makefile | 1 +
arch/arm/cpu/armv7/uniphier/board_early_init_f.c | 22 ++
ar
Masahiro Yamada (7):
ARM: UniPhier: move pin_init() to board_early_init_f()
ARM: UniPhier: move SPL init functions to spl_board_init()
ARM: UniPhier: revive support card info
ARM: UniPhier: remove unused checkboard() functions
ARM: UniPhier: do not compile unnecessary objects
ARM: Un
Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), the support card information has not been
displayed because check_support_card() is invoked only when
show_board_info() fails to get the model name from Device Tree.
This commit adds misc_init_f() function to call ch
Now init functions called from board_postclk_init() and dram_init()
are only necessary for SPL.
Move them to spl_board_init() for clean-up.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv7/uniphier/Makefile | 1 -
arch/arm/cpu/armv7/uniphier/board_postclk_init.c | 44 -
This EEPROM chip is installed on the expansion board commonly used
on UniPhier platform. To avoid duplicated description, move the
EEPROM node to a separate file and include it from other device tree
sources.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Fix the year of the credit block
To boot UniPhier boards with the NAND boot mode, two images
(u-boot-spl.bin and u-boot-dtb.img) must be written at the correct
offset addresses.
TFTP downloading is useful to update such images in the NAND device.
We generally do:
=> nand erase 0 0x10
=> tftpboot u-boot-spl.bin
=> nand
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Add more information
doc/README.uniphier | 85 +
1 file changed, 85 insertions(+)
create mode 100644 doc/README.uniphier
diff --git a/doc/README.uniphier b/doc/README.uniphier
new file mo
From: Raul Cardenas
Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protect
Masahiro Yamada (6):
ARM: UniPhier: use "&&" instead of ";" in commands
ARM: UniPhier: add environment variable to update images in NAND
ARM: UniPhier: add a simple README file for UniPhier platform
MAINTAINERS: claim maintainership of files with "uniphier" pattern
ARM: UniPhier: move EEP
Run the next command only when the previous one succeeded.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Newly added
include/configs/uniphier.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 9
The EEPROM chips on UniPhier reference daughter boards expect 2-byte
offset address.
Since 7132b9fd68a1 (dm: i2c: dts: Support an offset-len device tree
property), I2C sub-nodes can have "u-boot,i2c-offset-len" property.
It is convenient to set the default I2C offset address length in
Device Tree
The pattern "N:uniphier" can cover
- drivers/serial/serial_uniphier.c
- drivers/i2c/i2c-uniphier.c
- drivers/i2c/i2c-uniphier-f.c
- arch/arm/dts/uniphier-*
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- update git description
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+
On 24 January 2015 at 23:11, Masahiro Yamada wrote:
>
> This series can be applied on the current u-boot/master
> (commit 37b608a52dcb133)
>
> Buildman test passed.
>
> $ tools/buildman/buildman -s -b mach arm
> boards.cfg is up to date. Nothing to do.
> Summary of 22 commits for 474 boards (8 thr
If the i2c driver returns an error status, error out immediately.
Continuing the loop just results in printing error messages
again and again.
Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Cc: Heiko Schocher
---
common/cmd_i2c.c | 26 +-
1 file changed, 13 insertions(
Hi Akshay,
On 02/04/2015 07:29 PM, Akshay Saraswat wrote:
> This patch series does following changes -
> 1. Removing compiler warnings for clock_get_periph_rate.
> 2. Adding and enabling support for Exynos542x in
>clock_get_periph_rate.
> 3. Replacing peripheral specific function calls with
>
Hi Akshay,
On 02/04/2015 07:30 PM, Akshay Saraswat wrote:
> Since we have src, div and pre-div mask bits defined corresponding
> to peripherals, calculation of clock specific to I2C appears
> redundant and confusing. Using clk_bit_info struct we can write
> calculations generic to all peripherals
Hi,
On 3 February 2015 at 05:57, André Schaller wrote:
> Hi all,
>
> during the execution of th MLO I create a variable, whose value I want
> to make accessible to user space applications in Android. How can this
> be achieved?
>
> One way would be to write the contents of the variable to externa
If you want to inspect the control device tree using the fdt command,
the "fdt address -c" command previously unhelpfully printed the phys
memory address of the device tree. That address could not then be used
to set the fdt address for inspection. Changed the resulting print to
one that can be cop
Commit 90bac29a76bc8d649b41a55f2786c0abef9bb2c1 claims to fix this bug
that was introduced in commit a92fd6577ea17751ead9b50243e3c562125cf581
but doesn't actually make the change that the commit message describes.
Actually fix the bug this time.
Signed-off-by: Joe Hershberger
---
Changes in v3
Hi Jeroen,
On 4 February 2015 at 12:37, Jeroen Hofstee wrote:
> Hello Guilherme / Simon,
>
> It seems that commit f86ed6a8d52c99bb2d17d3cac1647edca0c4399c,
> "tools: moved code common to all image tools to a separated module."
>
> cause some trouble when building on FreeBSD.
>
> /usr/bin/ld:./too
On 4 February 2015 at 01:26, Bin Meng wrote:
> Add some instructions about building U-Boot for Intel Galileo board.
>
> Signed-off-by: Bin Meng
>
> ---
>
> doc/README.x86 | 24
> 1 file changed, 20 insertions(+), 4 deletions(-)
Acked-by: Simon Glass
___
On 4 February 2015 at 01:26, Bin Meng wrote:
> Intel Galileo board has a microSD slot which is routed from Quark SoC
> SDIO controller. Enable SD/MMC support so that we can use an SD card.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/quark/quark.c | 11 +++
> include/configs/galile
On 4 February 2015 at 01:26, Bin Meng wrote:
> The Quark SoC contains a legacy SPI controller in the legacy bridge
> which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
> control register offset in the ICH SPI driver is wrong for the Quark
> SoC too, unprotect_spi_flash() is added t
On 4 February 2015 at 01:26, Bin Meng wrote:
> Add pci ids for Intel Quark SoC.
>
> Signed-off-by: Bin Meng
> ---
>
> include/pci_ids.h | 4
> 1 file changed, 4 insertions(+)
Acked-by: Simon Glass
___
U-Boot mailing list
U-Boot@lists.denx.de
htt
On 4 February 2015 at 01:26, Bin Meng wrote:
> Quark SoC has some non-standard BARs (excluding PCI standard BARs)
> which need be initialized with suggested values. This includes GPIO,
> WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/
On 4 February 2015 at 01:26, Bin Meng wrote:
> Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
> which is just the same one found in other x86 chipset. Since we
> programmed the GPIO register block base address, we should be
> able to enable the GPIO support on Intel Galileo board
On 4 February 2015 at 20:16, Chris Kuethe wrote:
> Discovered while experimenting with signature checking on vexpress
> which doesn't typically use DM.
> ---
> Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Simon Glass
___
U-Boot mailing li
Hi,
On 28 January 2015 at 03:51, Gaurav Rana wrote:
> Currently only normal hashing is supported using hardware acceleration.
> Added support for progressinve hashing using h/w.
>
> Signed-off-by: Ruchika Gupta
> Signed-off-by: Gaurav Rana
> CC: Simon Glass
> ---
> This patch is dependent on f
Discovered while experimenting with signature checking on vexpress
which doesn't typically use DM.
---
Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/Kconfig b/Kconfig
index fed488f..8090790 100644
--- a/Kconfig
+++ b/Kconfig
@@ -118,6 +118,7 @@ config FIT_VERBOSE
config FIT_SIGNATUR
Hi Michal,
On 3 February 2015 at 17:40, Simon Glass wrote:
> Hi Michal,
>
> On 3 February 2015 at 02:11, Michal Simek wrote:
>> Hi Simon,
>>
>> On 02/03/2015 03:02 AM, Masahiro Yamada wrote:
>>> Hi.
>>>
>>>
>>> On Mon, 2 Feb 2015 16:57:15 -0700
>>> Simon Glass wrote:
>>>
Hi Michal,
>>
On 4 February 2015 at 05:05, Hans de Goede wrote:
> All callers of malloc should already do error checking, and may even be able
> to continue without the alloc succeeding.
>
> Moreover, common/malloc_simple.c is the only user of .rodata.str1.1 in
> common/built-in.o when building the SPL, trigger
On 4 February 2015 at 05:05, Hans de Goede wrote:
> common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
> Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes, and
> .data from 0x54c to 0x144 bytes.
>
> Signed-off-by: Hans de Goede
> ---
> include/config
On 4 February 2015 at 05:05, Hans de Goede wrote:
> Before this patch malloc_simple would always allocate a chunk of RAM from
> the stack. This commit adds a CONFIG_SYS_MALLOC_F_BASE define, which when
> set directly specifies the memory address to use for the heap with
> malloc_simple.
>
> Signed
On 4 February 2015 at 05:05, Hans de Goede wrote:
> Move the dram helper functions to a separate C file, rather then having them
> as inline helpers in dram.h. This saves 144 bytes in the .text segment for
> sun6i builds.
>
> Signed-off-by: Hans de Goede
> ---
> arch/arm/cpu/armv7/sunxi/Makefile
Hi Albert,
On 4 February 2015 at 01:48, Albert ARIBAUD wrote:
> Hello Tom,
>
> On Mon, 2 Feb 2015 13:56:57 -0500, Tom Rini wrote:
>
>> And (and this is being split into
>> different email threads, sigh), it would be good, possibly, if we have
>> something that means "very early init things, but
Hi Hans,
On 4 February 2015 at 01:47, Hans de Goede wrote:
> Hi,
>
> On 04-02-15 05:18, Simon Glass wrote:
>>
>> (What does FEL stand for?)
>>
>> This is an attempt to make sunxi's FEL code fit with the normal U-Boot
>> boot sequence instead of creating its own.
>>
>> Most of the FEL special-case
Hi Albert,
On 4 February 2015 at 01:57, Albert ARIBAUD wrote:
> Hello Simon,
>
> (sorry for the dupe)
>
> On Tue, 3 Feb 2015 21:18:50 -0700, Simon Glass
> wrote:
>
>> Allow r0 to be used for other purposes in this file.
>
> These purposes should be made clear -- possibly even, merged with the
>
Hi Albert,
On 4 February 2015 at 01:59, Albert ARIBAUD wrote:
> Hello Simon,
>
> On Tue, 3 Feb 2015 21:18:52 -0700, Simon Glass
> wrote:
>> The link register value can be required on some boards (e.g. FEL mode on
>> sunxi) so stash it to r4 before jumping to save_boot_params().
>
> I'd rather n
Hi Albert,
On 4 February 2015 at 01:50, Albert ARIBAUD wrote:
> Hello Simon,
>
> On Tue, 3 Feb 2015 21:18:51 -0700, Simon Glass
> wrote:
>> Some boards want to skip the normal reset init. For example OMAP4 SPL
>> does not want to touch VBAR and many boards don't want to set up
>> CP15.
>>
>> Pr
Hi Albert,
On 3 February 2015 at 10:13, Albert ARIBAUD (3ADEV)
wrote:
> This patch extends OMAP3 support for AM/DM37xx and
> introduces the AM3703-based Quipos Cairo board.
>
> Signed-off-by: Albert ARIBAUD (3ADEV)
> ---
> NOTES:
>
> Two checkpatch diagnostics are left uncorrected:
>
> 1. "warni
On 3 February 2015 at 18:04, Joe Hershberger wrote:
> If you want to inspect the control device tree using the fdt command,
> the "fdt address -c" command previously unhelpfully printed the phys
> memory address of the device tree. That address could not then be used
> to set the fdt address for i
On 3 February 2015 at 18:04, Joe Hershberger wrote:
> Commit 90bac29a76bc8d649b41a55f2786c0abef9bb2c1 claims to fix this bug
> that was introduced in commit a92fd6577ea17751ead9b50243e3c562125cf581
> but doesn't actually make the change that the commit message describes.
>
> Actually fix the bug t
Hi Simon,
On Thu, Feb 5, 2015 at 12:25 AM, Simon Glass wrote:
> Hi Bin,
>
> On 3 February 2015 at 04:45, Bin Meng wrote:
>> Now that we have added Quark MRC codes, call MRC in dram_init() so
>> that DRAM can be initialized on a Quark based board.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> a
Hi Simon,
On Thu, Feb 5, 2015 at 12:25 AM, Simon Glass wrote:
> Hi Bin,
>
> On 3 February 2015 at 04:45, Bin Meng wrote:
>> Turn on the Memory Reference code build in the quark Makefile.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> arch/x86/cpu/quark/Makefile | 1 +
>> 1 file changed, 1 insertio
The cause of a reset is generally useful, and shouldn't be
blindly cleared in the process of displaying it as a part
of the boot announcement.
If a particular system wants to clear it out, this should
be done later after there's an opportunity for code or
boot commands to read the value.
Signed-o
Hi Chris,
On 4 February 2015 at 00:47, Albert ARIBAUD wrote:
> Hello Simon,
>
> On Tue, 3 Feb 2015 18:01:49 -0700, Simon Glass wrote:
>> Hi Chris,
>>
>> On 3 February 2015 at 17:57, Chris Kuethe wrote:
>> > On Tue, Feb 3, 2015 at 4:38 PM, Simon Glass wrote:
>> >> +Masahiro
>> >>
>> >> Hi Chris
+Bin
Hi Gabriel,
On 4 February 2015 at 12:22, Gabriel Huau wrote:
> Hi All,
>
> I'm currently thinking on how to integrate the ACPI support in u-boot x86.
> I've investigated the coreboot implementation. My first thought was to port
> all the source code over but looking at the source code in mo
Hi All,
I'm currently thinking on how to integrate the ACPI support in u-boot
x86. I've investigated the coreboot implementation. My first thought was
to port all the source code over but looking at the source code in more
details it doesn't look like an easy option. For example, it involves
Hello Guilherme / Simon,
It seems that commit f86ed6a8d52c99bb2d17d3cac1647edca0c4399c,
"tools: moved code common to all image tools to a separated module."
cause some trouble when building on FreeBSD.
/usr/bin/ld:./tools/imagetool.lds:24: syntax error
cc: error: linker command failed with exit
Hello Albert,
thanks for the information. Do you mean to pass the value using an
environment variable to the boot parameter? How would I approach to set
up an environment variable in the SPL? Wouldn't it increase the memory
footprint such that the SPL wouldn't fit into SRAM anymore?
Best,
André
Dear Jean-Christophe Lallemand,
In message <9fddf58442d8154dbf9bb9a68ce7ad9cec6e3f1...@chuck.dvlt.local> you
wrote:
>
> I've stumbled upon SPL in my search for a good solution but my impression was
> that all the image loading stuff and therefore validation was not in there.
So add it?
> So I
On 02/04/2015 01:27 AM, Ian Campbell wrote:
On Wed, 2015-02-04 at 00:43 +0100, Hans de Goede wrote:
The recent changes to config_distro_bootcmd.h require CONFIG_CMD_PART to be
defined, as the default bootcmd not uses the "part" command.
^w
Shouldn't config_d
Dear Jean-Christophe Lallemand,
In message <9fddf58442d8154dbf9bb9a68ce7ad9cec6e3f1...@chuck.dvlt.local> you
wrote:
>
> What I'd like to do is have the already available u-boot (say Level-1) to
> load a second u-boot (say Level-2) into DDR where size is not an issue which
> will then load Linux
Hi Bin,
On 3 February 2015 at 04:45, Bin Meng wrote:
> Now that we have added Quark MRC codes, call MRC in dram_init() so
> that DRAM can be initialized on a Quark based board.
>
> Signed-off-by: Bin Meng
>
> ---
>
> arch/x86/cpu/quark/dram.c | 97
>
On 3 February 2015 at 04:45, Bin Meng wrote:
> Add standard dt-bindings macros to be used by Intel Quark MRC node.
>
> Signed-off-by: Bin Meng
> ---
>
> include/dt-bindings/mrc/quark.h | 83
> +
> 1 file changed, 83 insertions(+)
> create mode 100644 inc
Hi Bin,
On 3 February 2015 at 04:45, Bin Meng wrote:
> Add various utility codes needed for Quark MRC.
>
> Signed-off-by: Bin Meng
>
> ---
> There are 12 checkpatch warnings in this patch, which are:
>
> warning: arch/x86/cpu/quark/mrc_util.c,1446: Too many leading tabs - consider
> code refact
On 3 February 2015 at 04:45, Bin Meng wrote:
> For some unknown reason, the TSC calibration via PIT does not work on
> Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ
> to 400 per Quark datasheet in the Kconfig.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/quark/Kconfi
On 3 February 2015 at 04:45, Bin Meng wrote:
> We should allow the value of TSC_FREQ_IN_MHZ to be overridden by
> the one in arch/cpu//Kconfig.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/Kconfig | 40
> 1 file changed, 20 insertions(+), 20 deletions(-
Hi Bin,
On 3 February 2015 at 04:45, Bin Meng wrote:
> Add the main routines for Quark Memory Reference Code (MRC).
>
> Signed-off-by: Bin Meng
>
> ---
> The are 24 checkpatch warnings in this patch, which is:
>
> warning: arch/x86/cpu/quark/mrc.c,43: line over 80 characters
> ...
>
> I intentio
Hi Bin,
On 3 February 2015 at 04:45, Bin Meng wrote:
> Turn on the Memory Reference code build in the quark Makefile.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/quark/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makef
On 3 February 2015 at 04:45, Bin Meng wrote:
> Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can
> decode Intel Quark MRC node.
>
> Signed-off-by: Bin Meng
> ---
>
> include/fdtdec.h | 1 +
> lib/fdtdec.c | 1 +
> 2 files changed, 2 insertions(+)
Acked-by: Simon Glass
_
Hello;
I just started working with the ChiliSOM module [1] -- in my particular
case it is part of the Chiliboard [2].
The ChiliSOM is a nice little module based on the TI AM335x ARM SoC. I
already started porting the mainline U-boot for it. The DRAM and serial
console seem to work so far. I hope th
Dear all,
I have already used u-boot several times on various ARM-based platforms but I
need to go to unknown territories this time.
On an ARM-based platform again, we have a u-boot port (v2010.09) available
loaded by a ROM bootloader into the internal RAM.
For some reasons, the ROM bootloader l
On 2 February 2015 at 07:35, Bin Meng wrote:
> Add minimum codes to support Intel Quark SoC. DRAM initialization
> is not ready yet so a hardcoded gd->ram_size is assigned.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - Add simple help for ACPI PM1, PBLK and GEP0
>
> Changes in v2:
>
On 2 February 2015 at 07:35, Bin Meng wrote:
> Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
> initialized by hardware. eSRAM is the ideal place to be used
> for Cache-As-RAM (CAR) before system memory is available.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - Use macro
On 2 February 2015 at 07:35, Bin Meng wrote:
> device.h for integrated pci devices' bdf on Quark SoC and quark.h for
> various memory-mapped and i/o-mapped base addresses within SoC.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - Add several macros for message bus port and registers
>
On 2 February 2015 at 07:35, Bin Meng wrote:
> Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to
> arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these
> macros can be used for pci configuration space access.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> -
On 3 February 2015 at 01:27, Akshay Saraswat wrote:
> We have assumed and kept mask bits for divider and pre-divider
> as 0xf and 0xff, respectively. But these mask bits change from
> one peripheral to another, and hence, need to be specified in
> accordance with the peripherals.
>
> Signed-off-by
On 3 February 2015 at 01:19, Akshay Saraswat wrote:
> From: Doug Anderson
>
> It was found that the L2 cache timings that we had before could cause
> freezes and hangs. We should make things more robust with better
> timings. Currently the production ChromeOS kernel applies these
> timings, but
On 3 February 2015 at 01:18, Akshay Saraswat wrote:
> This patch adds code to shutdown secondary cores.
> When U-boot comes up, all secondary cores appear powered on,
> which is undesirable and causes side effects while
> initializing these cores in kernel.
>
> Secondary core power down happens in
hi Linus,
The following is some advice about the multi entry patch.
> While the Freescale ARMv8 board LS2085A will enter U-Boot both
> on a master and a secondary (slave) CPU, this is not the common
> behaviour on ARMv8 platforms. The norm is that U-Boot is entered
> from the master
Hello!
On 2015-02-04 11:42, Albert ARIBAUD wrote:
Hello Tobias,
You should use git send-email (or better yet, patman) for sending
patches; this one was attached instead of inline.
Sorry, I normally do that, but I didn't have access to my Odroid system
when I sent the patch.
That being said
On Mon 2015-02-02 10:18:23, Stephen Warren wrote:
> On 01/31/2015 08:20 PM, Simon Glass wrote:
> >Hi Albert,
> >
> >On 31 January 2015 at 20:02, Albert ARIBAUD
> >wrote:
> >>Hello Masahiro,
> >>
> >>On Sun, 25 Jan 2015 15:11:02 +0900, Masahiro Yamada
> >> wrote:
> >>>
> >>>This series can be appl
Hi all,
is it possible to start FIT signed kernel from SPL (falcon mode)?
Thanks,
marek
--
as simple and primitive as possible
-
Marek Belisko - OPEN-NANDRA
Freelance Developer
Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
Tel: +421 915 052
On Fri 2015-01-30 23:08:46, Marek Vasut wrote:
> Since all boards now have a DT, instead of hard-coding the board
> name into the U-Boot binary, read the board name from DT "model"
> property.
>
> Signed-off-by: Marek Vasut
> Cc: Chin Liang See
> Cc: Dinh Nguyen
Acked-by: Pavel Machek
--
(en
On Sat 2015-01-17 03:39:46, Marek Vasut wrote:
> On Friday, January 16, 2015 at 08:04:20 PM, Pavel Machek wrote:
> > Hi!
>
> Hi!
>
> > > > +void wait_di_buffer(void)
> > > > +{
> > > > + if (debug_data->di_report.cur_samples == NUM_DI_SAMPLE) {
> > > > + debug_data->di_report.
Hi Albert,
On 04/02/15 21:29, Albert ARIBAUD wrote:
Hello Graeme,
On Wed, 04 Feb 2015 18:14:22 +1100, Graeme Russ
wrote:
So the first question that we need to answer is: Do the avr32, m68k,
nds32, and sparc toolchains support the generation of the relevant
sections needed to perform reloca
Hi Albert,
If we use SPL, we do not have to relocate code, I think.
SPL doesn't have relocation that's why this code is not used there.
It is not what I meant.
If SPL can directly load the main u-boot image
to the DRAM address where it is linked,
we do not relocate the code in the main
Move the dram helper functions to a separate C file, rather then having them
as inline helpers in dram.h. This saves 144 bytes in the .text segment for
sun6i builds.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/dram_helpers.c | 37
common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes, and
.data from 0x54c to 0x144 bytes.
Signed-off-by: Hans de Goede
---
include/configs/sunxi-common.h | 5 +++--
1 file changed, 3 insertions(+), 2 d
Before this patch malloc_simple would always allocate a chunk of RAM from
the stack. This commit adds a CONFIG_SYS_MALLOC_F_BASE define, which when
set directly specifies the memory address to use for the heap with
malloc_simple.
Signed-off-by: Hans de Goede
---
arch/arm/lib/crt0.S | 2 +-
commo
Hi All,
Inspired by Simon's work to make the FEL SPL and regular SPL builds more
similar I've been looking into reducing the size of the SPL, resulting in
the following patch series. This all seems quite safe, but we are past rc1,
so may be best to keep this on a branch for now, or not ...
Simon,
All callers of malloc should already do error checking, and may even be able
to continue without the alloc succeeding.
Moreover, common/malloc_simple.c is the only user of .rodata.str1.1 in
common/built-in.o when building the SPL, triggering this gcc bug:
https://gcc.gnu.org/bugzilla/show_bug.cgi?
Hi Albert,
On 02/04/2015 11:34 AM, Albert ARIBAUD wrote:
> Hello Michal,
>
> On Wed, 4 Feb 2015 10:56:02 +0100, Michal Simek
> wrote:
>> On 02/04/2015 04:11 AM, Masahiro Yamada wrote:
>>> Hi Michal,
>>>
>>>
>>> On Tue, 3 Feb 2015 10:11:39 +0100
>>> Michal Simek wrote:
>>>
Hi Simon,
>>
On 04/02/15 10:15, Peng Fan wrote:
> If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined,
> smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr(
> _smp_pen), before code is relocated to secure ram.
> So need relocation to secure ram before enable secon
Hi Anatolij,
On Tue, 3 Feb 2015 20:17:36 +0100
Anatolij Gustschin wrote:
> Hello Boris,
>
> On Tue, 3 Feb 2015 19:39:16 +0100
> Boris Brezillon wrote:
>
> > Hello,
> >
> > I'm currently porting the SECO iMX6 uQ7 board to mainline, but I'm
> > facing a hang when enabling DCache (CONFIG_SYS_DC
Hello Tobias,
You should use git send-email (or better yet, patman) for sending
patches; this one was attached instead of inline.
That being said, it did not seem to worry patchwork, so you don't
need to repost this one.
Amicalement,
--
Albert.
___
U-
Hello Michal,
On Wed, 4 Feb 2015 10:56:02 +0100, Michal Simek
wrote:
> On 02/04/2015 04:11 AM, Masahiro Yamada wrote:
> > Hi Michal,
> >
> >
> > On Tue, 3 Feb 2015 10:11:39 +0100
> > Michal Simek wrote:
> >
> >> Hi Simon,
> >>
> >> On 02/03/2015 03:02 AM, Masahiro Yamada wrote:
> >>> Hi.
> >>
Hello Graeme,
On Wed, 04 Feb 2015 18:14:22 +1100, Graeme Russ
wrote:
> Hi Guys,
>
> Since I did the initial 'full relocation' for x86 way back when
> (http://git.denx.de/?p=u-boot.git;a=commit;h=1c409bc7101a24ecd47a13a4e851845d66dc23ce),
>
> there has been a lot of chatter about the ongoing n
Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Using clk_bit_info struct we can write
calculations generic to all peripherals which makes code easy to
understand and free from peripheral specif
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of peripheral and SoC specific function
implementations which was used earlier for fetching peripheral clocks.
This code is not being used anymore bec
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat
---
Changes since v5:
- No Change.
C
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat
Reviewed-by: Simon Gla
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