On Sat, Jul 05, 2014 at 12:57:22AM +0200, Albert ARIBAUD wrote:
> Hello,
>
> The following changes since commit
> fe8b3212b7938861eacdefe6115810303a96f9cc:
>
> Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-07-02
> 16:38:02 -0400)
>
> are available in the git repository at:
>
Hello,
The following changes since commit
fe8b3212b7938861eacdefe6115810303a96f9cc:
Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-07-02
16:38:02 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-arm master
for you to fetch changes up to 4009bed4694892
Albert,
I don't think that there is any code currently submitted that triggers
this error.
(it is "hidden" inside inline functions...)
However, you could add one line of code 'anywhere' to test this:
test_and_set_bit(1, (volatile void *)0x12345678);
Thanks, Steve
PS.
- using:
gcc-li
Hi Chin,
On Tue, 10 Jun 2014 01:17:42 -0500, Chin Liang See
wrote:
> Scan Manager driver will be called to configure the IOCSR
> scan chain. This configuration will setup the IO buffer settings
>
> Signed-off-by: Chin Liang See
> Cc: Dinh Nguyen
> Cc: Wolfgang Denk
> CC: Pavel Machek
> Cc:
Hi Chin,
On Tue, 10 Jun 2014 01:10:21 -0500, Chin Liang See
wrote:
> To add the DesignWare watchdog driver support. It required
> information such as register base address and clock info from
> configuration header file within include/configs folder.
>
> Signed-off-by: Chin Liang See
> Cc: An
Hi Chin,
On Tue, 10 Jun 2014 01:11:04 -0500, Chin Liang See
wrote:
> To enable the DesignWare watchdog support at SOCFPGA
> Cyclone V dev kit.
>
> Signed-off-by: Chin Liang See
> Cc: Anatolij Gustschin
> Cc: Albert Aribaud
> Cc: Heiko Schocher
> Cc: Tom Rini
> ---
> Changes for v5
> - Upda
Hi Axel,
On Mon, 16 Sep 2013 08:35:41 +0800, Axel Lin
wrote:
> In current gpio_set_value() implementation, it always sets the gpio control
> bit
> no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
> This patch fixes this bug.
>
> The address bus is used as a mask on read
Hi Magnus,
On Fri, Jul 4, 2014 at 12:42 PM, Magnus Lilja wrote:
> Hi all,
>
> (I hope gmail formats this mail according to the mailing list requirements,
> my apologies if it doesn't)
I think that HTML is forbidden. You can switch Gmail to plain text
mode with the "More options" down arrow in th
Hi Darwin,
On Mon, 9 Jun 2014 13:25:52 -0700, Darwin Rambo
wrote:
> From: "Shaibal.Dutta"
>
> Fix following compilation error when CONFIG_ARM64 is defined
>
> Error: unknown or missing system register name at operand 2
> -- `mrs x0,daifmsr daifset,#3'
>
> Signed-off-by: Shaibal.Dutta
> Sign
Hi Albert,
On Fri, Jul 4, 2014 at 10:50 AM, Albert ARIBAUD
wrote:
> On Thu, 3 Jul 2014 22:58:56 +0200, Benoît Thébaudeau
> wrote:
>> On Thu, Jul 3, 2014 at 3:35 PM, Albert ARIBAUD
>> wrote:
>> > On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger
>> > wrote:
>> >> On 07/03/2014 01:20 AM, Benoît
Tested-by: Steve Rae
(does resolve the issue on our board!)
On 14-06-27 02:37 AM, Pantelis Antoniou wrote:
Hi Eli,
On Jun 12, 2014, at 12:41 PM, Eli Billauer wrote:
The current wait loop just reads the status 1 times, which makes the
actual timeout period platform-dependent. The udelay(
Hi Christian,
On Wed, 2 Jul 2014 15:45:17 +0200, Christian Riesch
wrote:
> Hello Albert,
>
> On Wed, Jun 18, 2014 at 2:55 PM, Christian Riesch
> wrote:
> > Am I missing something here? What would be the preferred solution to
> > make the board working again?
>
> Any comments on this? What sha
Add documentation for dns-320 dns-325 kirkwood box.
This documentation include harware description, and link to external
documentation.
Signed-off-by: Bastien ROUCARIÈS
---
doc/README.dnskw | 25 +
1 file changed, 25 insertions(+)
create mode 100644 doc/README.dnskw
d
From: Jamie Lentin
Neither device makes any use of the SD reader functionalty, so as
suggested by Stefan Herbrechtsmeier, set the pins to GPIO instead
to make this more obvious. Label MPP10 & MPP11's use whilst here.
Signed-off-by: Jamie Lentin
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud
From: Jamie Lentin
Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more
information on this NAS, see:-
http://jamie.lentin.co.uk/devices/dlink-dns320
http://dns323.kood.org/dns-320
http://sharecenter.dlink.com/products/DNS-320
Signed-off-by: Jamie Lentin
Cc: prafu...
From: Jamie Lentin
You should already know you're using a D-link device.
Signed-off-by: Jamie Lentin
---
include/configs/dnskw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/dnskw.h b/include/configs/dnskw.h
index e55fdc4..7058873 100644
--- a/include/con
From: Jamie Lentin
So we can re-use DNS-325 configuration for the DNS-320 without things getting
confusing, rename all common parts from dns325 to dnskw, and use a config
option to configure DNS-325 specifics.
Signed-off-by: Jamie Lentin
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud.net
--
Add a new kirkwook board dns-320.
This is a rebase of an old patch set from Jamie Lentin.
Source is available here:
http://jamie.lentin.co.uk/devices/dlink-dns325/
Please apply
Changelog:
[V2] Use git option -M
[V3] Fix a mismerge in boards.cfg
[V4] Rebase.
[V5] Add documentation
Cc: Prafulla W
Hi Albert,
On Mon, 9 Jun 2014 10:11:28 +0200, Albert ARIBAUD
wrote:
> Hi Anthony,
>
> On Wed, 14 May 2014 17:29:48 -0400, Anthony Felice
> wrote:
>
> > Removed settings in unsupported register fields. They didn’t
> > do anything, and in most cases, were not documented in the
> > reference man
Hi Prafulla,
On Fri, 4 Jul 2014 11:43:48 -0700, Prafulla Wadaskar
wrote:
>
>
> > -Original Message-
> > From: Luka Perkov [mailto:l...@openwrt.org]
> > Sent: 02 July 2014 05:48
> > To: u-boot@lists.denx.de
> > Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
> > Subject: [PATCH] A
This patch adds support for NAND device connected to GPMC chip-select on
following AM43xx EVM boards.
am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
controlled by:
(a) Statically usin
This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch,
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HI
This patch updates pin-mux for beaglebone NOR cape [1]
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes,
so only one of them can be enabled at a time from board profile configs.
[1] http://elinux.org/Bea
This patch moves some board specific NAND configs:
- FROM: generic config files like 'ti_armv7_common.h' and 'ti_am335x_common.h'
- TO: individual board config files using these configs.
So that each board can independently set the value as per its design.
Following configs are affected in this
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with
This patch
- consolidate CONFIG_SYS_NAND_xx and CONFIG_SPL_NAND_xx from various
configuration files into single file.
- update MTD Partition table to match AM335x_EVM DT in linux-kernel
- segregate CONFIGs based on different boot modes (like SPL and U-Boot)
Signed-off-by: Pekon Gupta
---
inclu
Most platforms have fall-back boot sources, if their primary boot fails.
This patch allows board_init to continue scanning through other secondary boot
sources like NAND, MMC, etc if valid FLASH device is not detected.
Signed-off-by: Pekon Gupta
---
arch/arm/lib/board.c | 7 +--
1 file chang
This patch series adds support for parallel NAND devices support connected via
GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms.
This series also moves some board specific CONFIG_NAND_xx from generic files
to individual files.
Tested using: ./MAKEALL -s am33xx -s omap3 -s
Hi Bastien,
On Fri, 4 Jul 2014 19:01:48 +0200, Bastien ROUCARIÈS
wrote:
> From: Jamie Lentin
>
> Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more
> information on this NAS, see:-
>
> http://jamie.lentin.co.uk/devices/dlink-dns320
> http://dns323.kood.org/dns-320
Hi Bastien,
On Fri, 4 Jul 2014 19:01:47 +0200, Bastien ROUCARIÈS
wrote:
> From: Jamie Lentin
>
> So we can re-use DNS-325 configuration for the DNS-320 without things getting
> confusing, rename all common parts from dns325 to dnskw, and use a config
> option to configure DNS-325 specifics.
>
> -Original Message-
> From: Luka Perkov [mailto:l...@openwrt.org]
> Sent: 02 July 2014 05:48
> To: u-boot@lists.denx.de
> Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
> Subject: [PATCH] ARM: kirkwood: fix cpu info for 6282
> device id
>
> Signed-off-by: Luka Perkov
> CC: Prafu
Hi Jeroen,
On Mon, 23 Jun 2014 22:07:04 +0200, Jeroen Hofstee
wrote:
> This is not only more readable but also prevents a warning
> about a missing prototype. The prototypes which are actually
> missing are added.
>
> cc: Albert Aribaud
> Signed-off-by: Jeroen Hofstee
> ---
> arch/arm/cpu/ar
Hi Tom,
On Mon, 23 Jun 2014 16:15:51 -0400, Tom Rini wrote:
> On Mon, Jun 23, 2014 at 10:07:04PM +0200, Jeroen Hofstee wrote:
>
> > This is not only more readable but also prevents a warning
> > about a missing prototype. The prototypes which are actually
> > missing are added.
> >
> > cc: Alb
Hi York,
On Mon, 23 Jun 2014 15:15:52 -0700, York Sun
wrote:
> From: "J. German Rivera"
>
> This is needed for accessing peripherals with 64-bit MMIO registers,
> from ARMv8 processors.
>
> Signed-off-by: J. German Rivera
> ---
> Change log
> v9: no change
> v8: no change
> v7: no change
From: Jamie Lentin
Neither device makes any use of the SD reader functionalty, so as
suggested by Stefan Herbrechtsmeier, set the pins to GPIO instead
to make this more obvious. Label MPP10 & MPP11's use whilst here.
Signed-off-by: Jamie Lentin
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud
From: Jamie Lentin
Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more
information on this NAS, see:-
http://jamie.lentin.co.uk/devices/dlink-dns320
http://dns323.kood.org/dns-320
http://sharecenter.dlink.com/products/DNS-320
Changes since V1:
* Shorten CONFIG_IDENT_
From: Jamie Lentin
You should already know you're using a D-link device.
Signed-off-by: Jamie Lentin
---
include/configs/dnskw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/dnskw.h b/include/configs/dnskw.h
index e55fdc4..7058873 100644
--- a/include/con
From: Jamie Lentin
So we can re-use DNS-325 configuration for the DNS-320 without things getting
confusing, rename all common parts from dns325 to dnskw, and use a config
option to configure DNS-325 specifics.
Signed-off-by: Jamie Lentin
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud.net
--
Add a new kirkwook board dns-320.
This is a rebase of an old patch set from Jamie Lentin.
Source is available here:
http://jamie.lentin.co.uk/devices/dlink-dns325/
Please apply
Changelog:
[V2] Use git option -M
[V3] Fix a mismerge in boards.cfg
[V4] Rebase.
Cc: Prafulla Wadaskar
Cc: Jamie Len
On Fri, 2014-07-04 at 17:44 +0200, Marek Vasut wrote:
> On Friday, July 04, 2014 at 05:26:40 PM, Ian Campbell wrote:
> > On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote:
> > > On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
> > > > In 73545f75b66d "ahci: wait longer for link" I i
On Friday, July 04, 2014 at 05:25:10 PM, Ian Campbell wrote:
> On Fri, 2014-07-04 at 16:59 +0200, Marek Vasut wrote:
> > On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote:
> > > This has been disabled for ARM in initr_scsi since that function was
> > > introduced. However it works fine f
On Friday, July 04, 2014 at 05:26:40 PM, Ian Campbell wrote:
> On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote:
> > On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
> > > In 73545f75b66d "ahci: wait longer for link" I increased the
> > > timeout to 40ms based on the observed behav
On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote:
> On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
> > In 73545f75b66d "ahci: wait longer for link" I increased the
> > timeout to 40ms based on the observed behaviour of a WD disk on a
> > Cubietruck. Since then Karsten Merker and
On Fri, 2014-07-04 at 16:59 +0200, Marek Vasut wrote:
> On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote:
> > This has been disabled for ARM in initr_scsi since that function was
> > introduced. However it works fine for me on Cubieboard and Cubietruck (with
> > the upcoming AHCI glue p
On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote:
> This has been disabled for ARM in initr_scsi since that function was
> introduced. However it works fine for me on Cubieboard and Cubietruck (with
> the upcoming AHCI glue patch).
Does this break bisectability ?
> I also tested on tw
On Friday, July 04, 2014 at 12:19:14 PM, Masahiro Yamada wrote:
> The driver for on-chip UART used on Panasonic UniPhier platform.
>
> Signed-off-by: Masahiro Yamada
[...]
> +static void uniphier_serial_init(struct uniphier_serial *port)
> +{
> + writeb(UART_LCR_WLS_8, &port->lcr);
> +
> +#
On Friday, July 04, 2014 at 12:19:13 PM, Masahiro Yamada wrote:
> The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
>
> This driver requires two CONFIG macros:
> - CONFIG_NAND_DENALI
> Define to enable this driver.
> - CONFIG_SYS_NAND_BAD_BLOCK_POS
> Specify bad
On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote:
> In 73545f75b66d "ahci: wait longer for link" I increased the
> timeout to 40ms based on the observed behaviour of a WD disk on a
> Cubietruck. Since then Karsten Merker and myself have both
> observed timeouts with HGST disks (Karsten
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/dts/exynos5420-peach-pit.dts | 30 ++
1 file changed
Enable drivers for FIMD, DP and parade bridge chip.
Signed-off-by: Ajay Kumar
---
include/configs/peach-pit.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 76b8d7a..88c093f 100644
--- a/include/configs/peach-pit.
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar
---
arch/arm/include/asm/arch-exynos/gpio.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/include/asm/arch-exynos/system.h |3 +
board/samsung/smdk5420/smdk5420.c | 129 +++--
2 files
From: Vadim Bendebury
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.
Signed-off-by: Vadim Bendebury
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
drivers/video/Makefile |1 +
drivers/v
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar
---
arch/arm/dts/exynos54xx.dts
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock.c | 83 +
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
Tested-by: Simon Glass
---
arch/arm/cpu/armv7/exynos/clock_init.h |3 +++
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +
2 files changed, 16 inser
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRE
Patchset V1:
https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html
Patchset V2:
https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html
Changes from V1:
[PATCH V2 3/10] : Don't mix cpu_is and proid_isas per Minkyu's suggestion.
Also, incorporate Simon's sugge
> -Original Message-
> From: Luka Perkov [mailto:l...@openwrt.org]
> Sent: 02 July 2014 05:47
> To: u-boot@lists.denx.de
> Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
> Subject: [PATCH] kirkwood: cosmetic: style fixes in
> kwbimage.cfg files
>
> When diffing through the various
> -Original Message-
> From: Luka Perkov [mailto:l...@openwrt.org]
> Sent: 02 July 2014 05:48
> To: u-boot@lists.denx.de
> Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
> Subject: [PATCH] kirkwood: ib62x0: add
> CONFIG_SYS_GENERIC_BOARD define
>
> Signed-off-by: Luka Perkov
> CC
> -Original Message-
> From: Luka Perkov [mailto:l...@openwrt.org]
> Sent: 02 July 2014 05:48
> To: u-boot@lists.denx.de
> Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
> Subject: [PATCH] kirkwood: define empty
> CONFIG_MVGBE_PORTS by default
>
> Each board with defines it's own
Hi York,
I spotted a couple of generic issues below. Most of these are issues
with the existing code that you happen to be moving around, rather than
with the new code this patch introduces.
There are a couple of gotchas around secondary startup that are painful
with the bootwrapper for arm64 at
Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.
Signed-off-by: Ivan Khoronz
Add support for NAND gpheader image. TI Keystone2 ROM bootloader
expects 8 bytes of trailing zeroes in the nand u-boot image.
So add zeros at the end of the nand gph image.
Acked-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk
---
Makefile | 6 ++
1 file changed, 6 insertions(+)
diff -
This series adds opportunity to write U-boot image on AEMIF NAND device
using standard nand u-boot commands. Also added script to automate this
process.
This series is logical continue of
"[U-boot] [Patch v3 0/3] keystone: nand: add additional nand ecclayout"
series (http://comments.gmane.org/gman
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.
On 07/04/2014 04:31 AM, Xiubo Li-B47053 wrote:
This patch series depends on the following patch:
[U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (
On 07/04/2014 04:48 AM, Xiubo Li-B47053 wrote:
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d639a6f..f090971 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARC
Hi all,
(I hope gmail formats this mail according to the mailing list requirements,
my apologies if it doesn't)
On 4 July 2014 10:50, Albert ARIBAUD wrote:
> Hi Benoît,
>
> On Thu, 3 Jul 2014 22:58:56 +0200, Benoît Thébaudeau
> wrote:
>
> > Hi Albert,
> > It makes sense to me. That should work
On 07/04/2014 05:08 PM, Przemyslaw Marczak wrote:
> On 07/04/2014 08:07 AM, Jaehoon Chung wrote:
>> On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
>>> This board file supports standard features of Odroid X2 and U3 boards:
>>> - Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set
Hi, Przemyslaw.
On 07/04/2014 05:07 PM, Przemyslaw Marczak wrote:
> Hello Jaehoon,
>
> On 07/04/2014 07:45 AM, Jaehoon Chung wrote:
>> Hi, Przemyslaw.
>>
>> On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
>>> It is possible to boot device using a micro SD or eMMC slots.
>>> In this situation, b
UniPhier is the SoC family developed by Panasonic Corporation,
based on ARM Cortex-A9.
This patch set adds its SoC/board support code with some drivers.
This series depends on the Denali NAND driver patch:
http://patchwork.ozlabs.org/patch/357717/
It must be applied first.
Masahiro Yamada (6)
Add board entries for Panasonic UniPhier family:
PH1-LD4, PH1-Pro4, PH1-sLD8
Signed-off-by: Masahiro Yamada
---
boards.cfg | 3 +++
1 file changed, 3 insertions(+)
diff --git a/boards.cfg b/boards.cfg
index 8e2db82..cfe4498 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -376,6 +376,9 @@ Active a
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
Signed-off-by: Masahiro Ya
Configuration headers for Panasonic UniPhier series:
PH1-LD4, PH1-Pro4, PH1-sLD8
Signed-off-by: Masahiro Yamada
---
include/configs/ph1_ld4.h | 64 +
include/configs/ph1_pro4.h| 66 +
include/configs/ph1_sld8.h| 64 +
include/configs/uniphier-c
The driver for on-chip UART used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada
---
drivers/serial/Makefile | 1 +
drivers/serial/serial.c | 2 +
drivers/serial/serial_uniphier.c | 206 +++
3 files changed, 209 insertions
Signed-off-by: Masahiro Yamada
---
doc/git-mailrc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index e53c888..77f66f9 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -26,6 +26,7 @@ alias lukma Lukasz Majewski
alias macpaulMacpaul Li
From: Tang Yuantian
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.
Signed-off-by: Tang Yua
On 07/04/2014 04:43 AM, Xiubo Li-B47053 wrote:
Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/03/2014 12:51 PM, Xiubo Li wrote:
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH
Timer's frequency.
Can you give an example?
In LS1021A-QDS/TWR, the CON
Hi,
Apologies for the late reply.
On Fri, Jun 27, 2014 at 05:44:05PM +0100, Tom Rini wrote:
> On Fri, Jun 27, 2014 at 09:11:39AM -0700, York Sun wrote:
>
> > Dear Albert, Wolfgang, Tom,
> >
> > I have seen some patches for PSCI. We don't have PSCI enabled on
> > Freescale ARMv8 SoCs. Will spin-
Hi Benoît,
On Thu, 3 Jul 2014 22:58:56 +0200, Benoît Thébaudeau
wrote:
> Hi Albert,
>
> On Thu, Jul 3, 2014 at 3:35 PM, Albert ARIBAUD
> wrote:
> > Hi Helmut,
> >
> > On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger
> > wrote:
> >
> >> Hi,
> >>
> >> On 07/03/2014 01:20 AM, Benoît Thébaudeau
On 07/04/2014 08:07 AM, Jaehoon Chung wrote:
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable X
On 07/04/2014 07:49 AM, Jaehoon Chung wrote:
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This change adds declaration of functions:
- set_board_type() - called at checkboard()
- get_board_type() - called at checkboard()
- get_board_name()
For supporting multiple board types in a one confi
Hello Jaehoon,
On 07/04/2014 07:45 AM, Jaehoon Chung wrote:
Hi, Przemyslaw.
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONF
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