Hi Raffaele,
On Thu, Mar 10, 2011 at 12:51 AM, Raffaele Recalcati
wrote:
> From: Raffaele Recalcati
>
> It is a recommended to check card status after these kind of commands.
> This is done using CMD13 (SEND_STATUS) JEDEC command.
> In case of error the previous command is issued again.
>
> Sign
Donghwa Lee
On 8 March 2011 16:11, Donghwa Lee wrote:
> This is common pwm driver of S5P.
>
> Signed-off-by: Donghwa Lee
> Signed-off-by: Kyungmin Park
> ---
> Changes since v3:
> - fixed pwm register offset
> - move definitions of register to header file
>
> Changes since v2:
> - Timer4 was bl
Hi Pandurang,
We solved this problem by using TLB mapping for U-Boot on our MIPS platforms.
This was also due to the fact that we need to load U-Boot at the top of
physical memory which is often unreachable with 32-bit addressing. By doing
this we always link U-Boot at address 0xC000 and it
common/update.c used to update flash with ITB image.
With this patch it can also use any templated nash commands to load and
save blobs.
Also it adds nand as possible target for update.
Usage example:
// to load itb from usb mass-storage device and save it into nand using
nash commands
setenv up
From: Raffaele Recalcati
Defining CONFIG_MMC_TRACE in the include board file it is possible to activate
a tracing support.
This code helps in case of eMMC hw failure or to investigate possible eMMC
initialization issues.
Signed-off-by: Raffaele Recalcati
---
drivers/mmc/mmc.c | 71 ++
From: Raffaele Recalcati
The first SEND_OP_COND (CMD1) is used only to ask card capabilities, waiting
that the card is not busy.
After it, an AND operation is done between card capabilities and host
capabilities, (at the moment only for the voltage field).
Finally the correct value is sent to the
From: Raffaele Recalcati
It is a recommended to check card status after these kind of commands.
This is done using CMD13 (SEND_STATUS) JEDEC command.
In case of error the previous command is issued again.
Signed-off-by: Raffaele Recalcati
---
drivers/mmc/mmc.c | 106 ++
I have added some better inizializations and status check.
I have created following patchset for Davinci dm365 against
git://arago-project.org/git/projects/u-boot-davinci.git git tree.
There are two commits more in that tree, but they are not
in conflict with my work.
I have finally tested this ser
Signed-off-by: Fabio Estevam
---
board/freescale/mx31pdk/mx31pdk.c | 25 -
1 files changed, 24 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mx31pdk/mx31pdk.c
b/board/freescale/mx31pdk/mx31pdk.c
index 4a5d3ef..0462a22 100644
--- a/board/freescale/mx31pdk/m
Signed-off-by: Fabio Estevam
---
board/freescale/mx31pdk/mx31pdk.c | 16
include/configs/mx31pdk.h |1 +
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx31pdk/mx31pdk.c
b/board/freescale/mx31pdk/mx31pdk.c
index a9f0fb4..4a5d3ef 100
I have an issue with i2c-1 bus speed not being calculated correctly on
MPC8377.
arch/powerpc/cpu/mpc83xx/speed.c lines 320+ are :
#if defined(CONFIG_MPC834x)
i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832x)
i2c1_clk
On Wed, Mar 9, 2011 at 9:36 AM, Kumar Gala wrote:
> the setting of pmuxcr? SW has to do that.
>
But we don't do this based off the switch value currently on
p1_p2_rdb_pc boards.
-M
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On Mar 9, 2011, at 12:38 AM, McClintock Matthew-B29882 wrote:
> On Sun, Mar 6, 2011 at 10:17 PM, Kumar Gala wrote:
>> + if (i2c_data & 0x1) {
>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
>> + puts("SD/MMC : 8-bit Mode\n");
>>
Hi Heiko,
> Maybe a way to go ... more comments?
>
> Below a patch, which introduces a function, which checks for
> "protection bugfixes", and if no bugfix is found the old code is
> executed. Just a fast RFC patch.
>
> bye,
> Heiko
>
> diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.
The current Mips CPU config.mk code always expects a Mips 4kc
core and toolchain. This is not appropiate for other toolchains
and CPUs/SoCs.
Replace the current MIPSFLAGS code by cc-option macro and use
-march=mips32r2 as default optimization level for all Mips32 CPUs.
Replace the endianess determ
From: Daniel Schwierzeck
Au1x00 is a SoC and its specific code should reside in an own
SoC subdirectory.
Signed-off-by: Daniel Schwierzeck
Shinya Kuribayashi
---
arch/mips/cpu/mips32/Makefile |2 -
arch/mips/cpu/mips32/au1x00/Makefile | 45
Purple is a SoC and its specific code should reside in an own
SoC subdirectory.
Signed-off-by: Daniel Schwierzeck
Shinya Kuribayashi
---
arch/mips/cpu/mips32/Makefile |1 -
arch/mips/cpu/mips32/purple/Makefile | 45
arch/mips/cpu/mips32/
IncaIP is a SoC and its specific code should reside in an own
SoC subdirectory.
Signed-off-by: Daniel Schwierzeck
Shinya Kuribayashi
---
arch/mips/cpu/mips32/Makefile|2 -
arch/mips/cpu/mips32/incaip/Makefile | 46 +++
arch/mips/cpu/mips32/incaip/asc_serial
This fixes a linker error introduced by the previous commit.
Signed-off-by: Daniel Schwierzeck
Cc: Shinya Kuribayashi
---
board/purple/u-boot.lds |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
index 719f268..982937d 10
All current Mips CPUs and SoCs are based on Mips32 arch. The complete
code resides in the global arch/mips/cpu directory. All SoC specific
code resides in this directory too. This is not suitable if other
Mips architectures like Mips64 or Octeon or new SoCs should be supported
in the future.
This
All current CPUs and SoCs are based on Mips32 arch. The complete
code resides in the global arch/mips/cpu directory. This is not
suitable if other Mips architectures like Mips64 or Octeon should
be supported in the future.
To achieve this the current CPU code is moved to its own mips32
subdirector
On Wednesday 09 March 2011 10:16 AM, John Rigby wrote:
> On Mon, Feb 28, 2011 at 4:46 AM, Aneesh V wrote:
>> Calculate EMIF register values based on AC timing parameters
>> from the SDRAM datasheet and the DDR frequency rather than
>> using the hard-coded values.
>>
>> For a new board the user doe
Add the first axi_ethernet driver for little-endian Microblaze.
Signed-off-by: Michal Simek
---
v2:
- Fix return addreses
- Fix NULL pointer defer for priv structure
v3:
- Freeing allocated memory when initialization failed
---
.../xilinx/microblaze-generic/microblaze-generic.c |4 +
drive
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