On Mar 9, 2011, at 12:38 AM, McClintock Matthew-B29882 wrote:
> On Sun, Mar 6, 2011 at 10:17 PM, Kumar Gala <ga...@kernel.crashing.org> wrote:
>> + if (i2c_data & 0x1) {
>> + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
>> + puts("SD/MMC : 8-bit Mode\n");
>> + puts("eSPI : Disabled\n");
>> + } else {
>> + puts("SD/MMC : 4-bit Mode\n");
>> + puts("eSPI : Enabled\n");
>
> I think this bit is actually important for the p1_p2_rdb_pc boards
> also? Is this handled by the CPLD somehow or do we need to do the same
> thing?
>
> 'IO0 - "read-only" CFG_SDWIDTH SW2[1].
the setting of pmuxcr? SW has to do that.
- k
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