Some old STMicro parts do not support JEDEC ID (0x9f). This patch
uses RES (0xab) to get Electronic ID and translates it to JEDEC ID.
Signed-off-by: Thomas Chou
---
drivers/mtd/spi/spi_flash.c | 12
drivers/mtd/spi/stmicro.c |8
2 files changed, 20 insertions(+), 0
Hi Kim,
On Monday 19 April 2010 22:52:34 Kim Phillips wrote:
> this patch is missing an update to the Directory Hierarchy section in
> the main README file. Other than that,
>
> Acked-by: Kim Phillips
OK, v4 will follow in a few minutes...
Thanks.
Cheers,
Stefan
--
DENX Software Engineering
Hi Wolfgang,
On Tuesday 20 April 2010 23:39:09 Wolfgang Denk wrote:
> > In order to eliminate redundant code for powerPC architecture when
> > defining post_word_{load/store} routines I suggest moving them into
> > the arch/ppc/lib/commproc.c file rather than adding them to every
> > arch/ppc/cpu
On Apr 20, 2010, at 11:15 PM, Kumar Gala wrote:
>
> On Apr 20, 2010, at 1:24 PM, Hillery, Nathan wrote:
>
>> I’m looking for U-boot support for the embedded SPI driver on the MPC8536 to
>> access a SPI flash device (Numonyx [ex-STmicro] M25P16). The eSPI can read
>> the SPI flash (that’s how
On Apr 20, 2010, at 1:24 PM, Hillery, Nathan wrote:
> I’m looking for U-boot support for the embedded SPI driver on the MPC8536 to
> access a SPI flash device (Numonyx [ex-STmicro] M25P16). The eSPI can read
> the SPI flash (that’s how U-boot gets loaded into RAM) and I can read/write
> from
This patch adds a status led driver followed the GPIO access
conventions of Linux. The led mask is used to specify the gpio pin.
Signed-off-by: Thomas Chou
---
Moved to drivers/misc.
drivers/misc/Makefile |1 +
drivers/misc/gpio_led.c | 30 ++
2 files changed
This is a generic approach to port u-boot for nios2 boards.
You may find the usage of this approach on the nioswiki,
http://nioswiki.com/DasUBoot
A fpga parameter file, which contains base address information
and drivers declaration, is generated from Altera's hardware system
description sopc file
On 04/21/2010 12:19 AM, Scott McNutt wrote:
>
> I don't think the Altera board tree is an appropriate place for
> code that supports custom logic blocks. If an Altera distribution
> provided a design that included this custom block in one of their
> board designs then it would probably be fine.
>
>
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0
On Tue, Apr 20, 2010 at 04:03:01PM -0600, Chris Rigg wrote:
> Thanks guys. I'll take a look at this in more depth. It sounds like this
> would be the suggested solution to my problem.
>
> Is there an example somewhere that you could point me towards?
>
As this is a bit off-topic on this list, I'
Thanks Wolfgang. Yes, I was intending to read from the host side while the
filesystem was active on the PPC (target) side. But after hearing back from
you guys and doing some more research it doesn't seem like a good (or even
workable) solution.
At this point, I'm thinking I'll design my own host-
Thanks guys. I'll take a look at this in more depth. It sounds like this
would be the suggested solution to my problem.
Is there an example somewhere that you could point me towards?
On Tue, Apr 20, 2010 at 3:37 PM, Scott McNutt wrote:
> Hi Chris,
>
> Ira W. Snyder wrote:
>
>> My problem:
>>> I
Dear Michael Zaidman,
In message <1271792672-10567-1-git-send-email-michael.zaid...@gmail.com> you
wrote:
> Defining the post_word_{load/store} routines in the ppc common code
> eliminates the necessity to redefine them for each of the ppc CPUs or
> boards.
>
> Signed-off-by: Michael Zaidman
>
Dear Chris Rigg,
In message you
wrote:
>
> My goal:
> I need a way to get the files from the ramdisk on the PPC to the host over
> PCI.
Design an interface. Or use an existing one.
> My solution:
> The best idea I could come up with was to map in the PPC's ramdisk memory on
> the host and then
On Tue, Apr 20, 2010 at 07:02:53PM +0200, Peter Vollmer wrote:
> I worked through that thread, but as it seems I have no unguarded memory
> range left. Each BAT entry has BATL_GUARDEDSTORAGE set.
> By using the BATL_CACHEINHIBIT for the RAM bock I suppose I have the
> dcache disabled, right?
H
Dear Michael Zaidman,
In message you
wrote:
>
> In order to eliminate redundant code for powerPC architecture when
> defining post_word_{load/store} routines I suggest moving them into
> the arch/ppc/lib/commproc.c file rather than adding them to every
> arch/ppc/cpu/.
NAK. The commproc.*
Hi Chris,
Ira W. Snyder wrote:
>> My problem:
>> If I have an in-memory filesystem on my board (the ramdisk), and I have the
>> entire 256MB of memory accessible to the host over the PCI bus, you'd think
>> I could write a tool (or find a tool) that I could point at a block of
>> physical memory a
On Sat, Apr 17, 2010 at 12:20 PM, Joakim Tjernlund
wrote:
>>
>> Michael Zaidman wrote on 2010/04/16 18:44:12:
>> >
>> > On Fri, Apr 16, 2010 at 1:25 AM, Kim Phillips
>> > wrote:
>> > > On Thu, 8 Apr 2010 10:37:08 +0200
>> > > Joakim Tjernlund wrote:
>> > >
>> > >> Kim Phillips wrote on 2010-04
On Tue, Apr 20, 2010 at 01:01:39PM -0600, Chris Rigg wrote:
> Hello,
>
> I have a general design question and I can't think of a better forum than
> this one to ask it in. Let me know if this is not the right place to ask.
>
> My environment:
> I have an embedded system (u-boot/Embedded Linux) ru
On Mon, Apr 19, 2010 at 7:44 PM, Michael Zaidman
wrote:
> Hi All,
>
> In order to eliminate redundant code for powerPC architecture when
> defining post_word_{load/store} routines I suggest moving them into
> the arch/ppc/lib/commproc.c file rather than adding them to every
> arch/ppc/cpu/.
>
>> Michael, can you resubmit something more comprehensive, something that
>> builds for 83xx with CONFIG_POST turned on?
>>
> Sure.
>
Please see this patch:
http://lists.denx.de/pipermail/u-boot/2010-April/070319.html
-michael
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* 128MB DDR2 SDRAM
* 256MB NAND
* 10/100 MBits Ethernet DP83848
* Serial number chip DS2401
The board is made as SODIMM200 module.
For more info www.ronatix.at or i...@ronetix.at.
Signed-off-by: Asen Dimov
---
MAINTAINERS
Defining the post_word_{load/store} routines in the ppc common code
eliminates the necessity to redefine them for each of the ppc CPUs or
boards.
Signed-off-by: Michael Zaidman
---
arch/ppc/lib/Makefile |1 +
arch/ppc/lib/commproc.c | 54 +++
2
Hello,
I have a general design question and I can't think of a better forum than
this one to ask it in. Let me know if this is not the right place to ask.
My environment:
I have an embedded system (u-boot/Embedded Linux) running on a PPC440 and
configured as a target over a PCI bus. My host is a
Dear USAA Customer,
As part of our security measures, we regularly screen activity in the USAA
system. We recently contacted you after noticing an issue on your account.
We requested information from you for the following reason:
We recently received a report of unauthorized credit card use ass
Thanks for all the valuable input. So this is what I have checked so far.
Until now the behaviour is still exactly as described in the first post.
On Tue, 20 Apr 2010 15:30:56 +0200, Joakim Tjernlund
wrote:
> Dunno, try running with any i/d cache for the DRAM. If that works
> it is very likel
Thomas Chou wrote:
> On 04/20/2010 09:19 PM, Scott McNutt wrote:
>>> +void __led_init(led_id_t mask, int state)
>>> +{
>>> +gpio_direction_output(mask, (state == STATUS_LED_ON) ? 0 : 1);
>>
>>
>> The direction register only exists when the PIO core hardware
>> is configured in bidirectional mod
On Apr 14, 2010, at 4:32 AM, Detlev Zundel wrote:
> This fixes an overflow during the link phase.
>
> Signed-off-by: Detlev Zundel
> ---
> include/configs/socrates.h |8
> 1 files changed, 4 insertions(+), 4 deletions(-)
applied to mpc85xx
- k
_
On Apr 14, 2010, at 6:05 AM, Dave Liu wrote:
> clean up the wrong io_sel for PCI express according to latest manual.
>
> Signed-off-by: Dave Liu
> ---
> arch/ppc/cpu/mpc8xxx/pci_cfg.c| 13 ++---
> arch/ppc/include/asm/immap_85xx.h |5 +
> 2 files changed, 11 insertions(+), 7
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.
Signed-off-by: Kumar Gala
---
arch/ppc/cpu/mpc83xx/serdes.c |2 +-
arch/ppc/include/asm/fsl_mpc
The new is_serdes_configured covers a broader range of devices than the
PCI specific code. Use it instead as we convert away from the
is_fsl_pci_cfg() code.
Signed-off-by: Kumar Gala
---
arch/ppc/cpu/mpc8xxx/pci_cfg.c| 12
board/freescale/mpc8536ds/mpc8536ds.c |7
On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.
Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabl
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala
---
arch/ppc/cpu/mpc85xx/mpc8536_serdes.c | 79 ++--
arch/ppc/in
This adds support for the AT91SAM9G20 boards by taskit GmbH.
Both boards, Stamp9G20 and PortuxG20, are integrated in one file.
PortuxG20 is basically a SBC built around Stam9G20.
Signed-off-by: Achim Ehrlich
---
MAINTAINERS|5 +
MAKEALL|
On 04/20/2010 09:19 PM, Scott McNutt wrote:
>> +void __led_init(led_id_t mask, int state)
>> +{
>> +gpio_direction_output(mask, (state == STATUS_LED_ON) ? 0 : 1);
>
>
> The direction register only exists when the PIO core hardware
> is configured in bidirectional mode.
> If the PIO core hardwa
Hi,
it seems I have found an unitialized variable when I run ubifsmount on
an ARM board.
The problem arises during the sget() function when the "type" of
filesystem is added to the superblock list, at the following line:
list_add(&s->s_instances, &type->fs_supers);
I have checked that f
After having customers complain about not being able to use some USB pen
drives,
we investigated this problem as well. To do so, we bought a sample of
eight USB pen
drives to catalog the partition tables of various keys in their "out of
the package" state. The contents of these drives are attached
"Peter Vollmer" wrote on 2010/04/20 14:12:41:
>
> On Tue, 20 Apr 2010 11:57:09 +0200, Joakim Tjernlund
> wrote:
> > Probably a BDI2000 issue. If memory serves right BDI2000 flushes the
> > cache when it hits a BP.
> >
> > Try this addin this to your BDI .cfg file:
> > TSZ40xe600 0xe6000
Thomas,
Thomas Chou wrote:
> This patch adds a gpio based status led driver. The led mask
> is used to specify the gpio pin.
>
> Signed-off-by: Thomas Chou
> ---
> board/altera/common/gpioled.c | 30 ++
> 1 files changed, 30 insertions(+), 0 deletions(-)
> create
Hi "zs",
> because my email box z...@hebut.edu.cn is little size,
> I do not want to receive email any more,
> please help me to Unsubscribe.
Just look at the footer of every message and you will find the URL to a
webinterface:
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.d
It sure looks like an mpc8313 problem I once looked into
for quite some time. The solution was:
http://lists.denx.de/pipermail/u-boot/2009-March/049175.html
It could also be your DDR RAM not properly functioning. You
can let u-boot test it with the POST MEM test (which happens
before relocation
Signed-off-by: Larry Johnson
---
board/korat/korat.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/korat/korat.c b/board/korat/korat.c
index d5260dc..e5ec694 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
Signed-off-by: Larry Johnson
---
common/cmd_bootm.c |7 ++-
common/image.c |3 +++
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 452686d..da06009 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -344,11 +344
Hi Tom,
On Sun, Apr 11, 2010 at 10:45:41PM +0200, Tom wrote:
> Rabin Vincent wrote:
> > On Fri, Apr 9, 2010 at 6:57 PM, Vaibhav Bedia
> > wrote:
> >> As all Cortex processors implement the ARMv7 architecture a better grouping
> >> IMHO would be cpu/cortex/a8 and cpu/cortex/a9. The common stuff c
On Tue, 20 Apr 2010 11:57:09 +0200, Joakim Tjernlund
wrote:
> Probably a BDI2000 issue. If memory serves right BDI2000 flushes the
> cache when it hits a BP.
>
> Try this addin this to your BDI .cfg file:
> TSZ40xe600 0xe60001100 ; init stack space for cache
> ; needs a 'sap 0' in BD
LinkedIn
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>
> On Tue, 20 Apr 2010 10:36:08 +0200, Peter Vollmer
> wrote:
>
>
> > I then inserted 8 pairs of lwzu/stwu inside the loop to see when exactly
> > the problem occurs:
> >
> > 1: lwzur0,4(r8)
> > stwur0,4(r7)
> > lwzur0,4(r8)
> > stwur0,4(r7)
> > ...
> > lwzu
Recent crc changes started using the "uint" type in headers that are used
on the build system. This subsequently broke mingw targets as they do not
provide such a type. So add this basic typedef to compiler.h so that we
do not have to worry about this breaking again in the future.
Signed-off-by:
Hi All,
At last all is done. There were plattform specific changes in the board.
Now I am able to run the CFI driver for flash chip S29GL512P.
Thanks for your help so far.
Regards,
Prakash
On Fri, Apr 16, 2010 at 8:08 PM, prakash bedge wrote:
> Hi,
>
>
>
> I removed the changes as you sugge
Hi Stevan,
On Monday 19 April 2010 22:32:56 Stevan Saban wrote:
> I am porting u-boot to a PPC 440EP custom board that is very similar to
> Yosemite.
>
> I have two chips (32 MB each) of NOR flash running through ECB at CS0
> and CS1 and using the CFI interface.
>
>
>
> I was wondering where u
On Tue, 20 Apr 2010 10:36:08 +0200, Peter Vollmer
wrote:
> I then inserted 8 pairs of lwzu/stwu inside the loop to see when exactly
> the problem occurs:
>
> 1: lwzur0,4(r8)
> stwur0,4(r7)
> lwzur0,4(r8)
> stwur0,4(r7)
> ...
> lwzur0,4(r8)
> stwu
Hi all,
I'm currently seeing a weird heisen-bug kind of problem on a mpc8313-based
board with large page NAND flash. The problem happens in u-boot-spl in
relocate_code. When I set a breakpoint after the first cycle of
...cpu/mpc83xx/start.S
relocate_code:
1: lwzur0,4(r8)
stwur0,4
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