> ---
> MAINTAINERS |1 +
> MAKEALL |1 +
> Makefile|3 +
> board/ti/sdp3430/Makefile | 49 ++
> board/ti/sdp3430/config.mk | 33
> board/ti/sdp3430/sdp.c | 194 ++
> board/ti/sdp3430/sd
Hi, everyone
I'm using u-boot for ARM9 S3C2410.
My tool chain is ELDK4.2.
I defined configuration "CONFIG_NAND_CMD,
CONFIG_SYS_MAX_NAND_DEVICE1,
and CONFIG_SYS_NAND_BASE 0x4E0C" for nand_init().
It works well until the routine reaches nand_scan() which is in nand_base.c
When nand_scan()
On Sat, 2009-09-19 at 10:37 -0500, Nishanth Menon wrote:
> Peter Tyser said the following on 09/19/2009 09:03 AM:
> > On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
> >
> >> This is questionable if this is really required
> >> as the av_ static initalized values should have
> >> been l
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> The sbc8548 has a 64MB SODIMM flash module off of CS6 that
> previously wasn't enumerated by u-boot. There were already
> BR6/OR6 settings for it [used by cpu_init_f()] but there
> was no TLB entry and it wasn't in the list of flash banks
> re
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> The get_clock_freq() comes from freescale/common/cadmus.c and is
> only valid for the CDS based 85xx reference platforms. It would
> be nice if we could read the 33 vs. 66MHz status somehow, but in
> the meantime, tie it to CONFIG_SYS_CLK_FREQ
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> There are a couple defines and PCI bridge quirks related to the PCI
> backplane of the MPC8548CDS that have no meaning in the context of
> the port to the sbc8548 board, so delete them.
>
> Also, the form factor of the sbc8548 is a standalone b
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> Create a board_eth_init to allow a place to hook in
> the PCI ethernet init after all the eTSEC are up
> and configured.
>
> Signed-off-by: Paul Gortmaker
> ---
> board/sbc8548/sbc8548.c |9 +
> 1 files changed, 9 insertions(+), 0 d
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> The previous README.sbc8548 was pretty much content-free. Replace
> it with something that actually gives the end user some relevant
> hardware details, and also lists the u-boot configuration choices.
>
> Also in the cosmetic department, fix t
On Sep 19, 2009, at 7:20 AM, Poonam Aggrwal wrote:
> The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/
> P2010
> where max DDR data width supported is 64bit.
> As a next step the DDR data width initialization would be made more
> dynamic
> with more flexibility from the boa
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms. Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks. We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities insid
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style. Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.
Signed-off-by: Kumar Gala
---
* Fix up for LAW_EN, and use LAW_S
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala
---
cpu/mpc85xx/Makefile|1 +
cpu/m
On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.
Signed-off-by: Kumar Gala
Signed-off-by: Scott Wood
---
* Fixup for LAW_EN
cpu/mpc85xx/cpu_init_early.c | 29 +
1 files changed, 29 insertion
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform. We reuse the 85xx immap and just add new definitions for
local access and global utils. The global utils is now broken into
global utils, clocking and run control/power management.
The offsets from CCSR for a numbe
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address. Also, the target IDs
on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala
---
* Fixed set_bits32 -> setbits_be32
board/freescale/mpc8572ds/mpc8572ds.c | 226 ++--
1 files c
General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.
Signed-off-by: Kumar Gala
---
* Fixed set_bits32 -> setbits_be32
board/freescale/p1_p2_rdb/pci.c | 42 --
drivers/pc
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala
---
* Fixed set_bits32 -> setbits_be32
board/freescale/p2020ds/p2020ds.c | 150 -
1 files
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> The size of the LB SDRAM on this board is 128MB, spanning CS3
> and CS4. It was previously only being configured for 64MB on
> CS3, since that was what the original codebase of the MPC8548CDS
> had. In addition to setting up BR4/OR4, this als
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> Prior to this commit, to enable PCI, you had to go manually
> edit the board config header, and if you had 33MHz PCI, you
> had to manually change CONFIG_SYS_NS16550_CLK too, which was
> not real user friendly,
>
> This adds the typical PCI and
On 85xx platforms we shouldn't be using any LAWAR_* defines
but using the LAW_* ones provided by fsl-law.h. Rename any such
uses and limit the LAWAR_ to the 83xx platform as the only user so
we will get compile errors in the future.
Signed-off-by: Kumar Gala
---
board/atum8548/law.c
On Sep 19, 2009, at 11:05 AM, Paul Gortmaker wrote:
> Kumar Gala wrote:
>> On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
>>> There are a couple defines and PCI bridge quirks related to the PCI
>>> backplane of the MPC8548CDS that have no meaning in the context of
>>> the port to the sbc8548
Kumar Gala wrote:
>
> On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
>
>> There are a couple defines and PCI bridge quirks related to the PCI
>> backplane of the MPC8548CDS that have no meaning in the context of
>> the port to the sbc8548 board, so delete them.
>>
>> Also, the form factor of
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms. Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks. We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities insid
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala
---
cpu/mpc85xx/Makefile|1 +
cpu/m
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style. Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.
Signed-off-by: Kumar Gala
---
cpu/mpc85xx/mp.c | 68 +
On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.
Signed-off-by: Kumar Gala
Signed-off-by: Scott Wood
---
* Updated based on LAWs being an array
cpu/mpc85xx/cpu_init_early.c | 29 +
1 files c
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform. We reuse the 85xx immap and just add new definitions for
local access and global utils. The global utils is now broken into
global utils, clocking and run control/power management.
The offsets from CCSR for a numbe
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address. Also, the target IDs
on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet
This patch add a MII Bus support for FCC port using a simple bitbang
implementation (derived from miiphy driver).
In order to enable mii bus, you need to define the following additional macros:
CONFIG_MPC85XX_BITBANGMII - Enable the mii bus support code
CONFIG_SYS_FCC1_MDIO - Pin used for MD
Signed-off-by: Luigi 'Comio' Mantellini
---
cpu/mpc85xx/ether_fcc.c | 400 ---
1 files changed, 379 insertions(+), 21 deletions(-)
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index 5f1414d..7d8234e 100644
--- a/cpu/mpc85xx/ether_fcc
From: Luigi 'Comio' Mantellini
Signed-off-by: Luigi 'Comio' Mantellini
---
cpu/mpc85xx/ether_fcc.c | 400 ---
1 files changed, 379 insertions(+), 21 deletions(-)
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index 5f1414d..7d8234e 1
From: Luigi 'Comio' Mantellini
This patch add a MII Bus support for FCC port using a simple bitbang
implementation (derived from miiphy driver).
In order to enable mii bus, you need to define the following additional macros:
CONFIG_MPC85XX_BITBANGMII - Enable the mii bus support code
CONFIG_SYS
Peter Tyser said the following on 09/19/2009 09:03 AM:
> On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
>
>> This is questionable if this is really required
>> as the av_ static initalized values should have
>> been loaded to sdram as part of the boot process
>> and initialization shou
Peter Tyser said the following on 09/19/2009 09:34 AM:
thanks for your review
> Hi Nishanth,
>
> On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
>
>> From: David Brownell
>>
>> Start of SDP3430 support in "mainline"
>> u-boot mainline code
>>
>> Original Patch written by David Brownell
This change adds some basic summary information to the MAKEALL script.
The summary information includes how many boards were compiled, how many
boards had compile warnings or errors, and which specific boards had
compile warnings or errors.
This information is useful when doing compile testing to
Hi Nishanth,
On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
> From: David Brownell
>
> Start of SDP3430 support in "mainline"
> u-boot mainline code
>
> Original Patch written by David Brownell
I don't think the above comments are necessary. David will be credited
with authorship al
On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
> This is questionable if this is really required
> as the av_ static initalized values should have
> been loaded to sdram as part of the boot process
> and initialization should have been done.
Is there a reason you need to do this fixup?
On Friday 18 September 2009 19:48:03 Peter Tyser wrote:
> + TOTAL_CNT=$(($TOTAL_CNT + 1))
what i suggested want a typo ;). you dont need to expand the var inside of
the $((...)). v=1; : $(( v += 1))
-mike
signature.asc
Description: This is a digitally signed message part.
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.
As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove
Hello, ALL:
I want use u-boot for lm3s811evb which emulated by QEMU system. But I
cannot file the related name from include/configs/ directory. I want to know
how I can configure the u-boot.
# make _config
Hope someone fill the name or give me idea how to compile u-boot to
support
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