Historical info (2012) says xchd is not used by sdcc for mcs51.
https://sourceforge.net/p/sdcc/discussion/1864/thread/08531ab9/
Regards,
Xiaofan
On Wed, 28 Jul 2021, 1:49 am , wrote:
> Hi,
>
> Currently I'm looking at making a sparse hardware re-implementation of
> an mcs51-like core. It does
Am 27.07.21 um 22:28 schrieb theo_sd...@borm.org:
> Hi, thanks
>
> The MCS51 has the JBC instruction, which tests a bit, jumps if its set
> and also clears the bit - all atomically. These would be perfect for
> atomic flags. In addition the MCS51 supports an array of XCH
> instructions which excha
Hi, thanks
The MCS51 has the JBC instruction, which tests a bit, jumps if its set
and also clears the bit - all atomically. These would be perfect for
atomic flags. In addition the MCS51 supports an array of XCH
instructions which exchange the full accumulator with a
register/sfr/memory locat
Am 27.07.21 um 19:49 schrieb theo_sd...@borm.org:
> Though I guess the XCHD opcodes had some use "back in the day",
I'm not an mcs51 expert, but I think these are the only efficient way to
implement somewhat-useable C11 atomic_flag on MCS-51.
Philipp
Hi,
Currently I'm looking at making a sparse hardware re-implementation of
an mcs51-like core. It does not have to be 100% binary compatible as
long as it can run compiled C code.
Two opcodes are a nuisance to implement in hardware:
0xd6/0xd7: XCHD A,(Rx)
these opcodes take the place of wh
