Am 27.07.21 um 22:28 schrieb theo_sd...@borm.org: > Hi, thanks > > The MCS51 has the JBC instruction, which tests a bit, jumps if its set > and also clears the bit - all atomically. These would be perfect for > atomic flags. In addition the MCS51 supports an array of XCH > instructions which exchange the full accumulator with a > register/sfr/memory location, and given the wider range of addressing > modes these would be a more useful alternative than the XCHD. > > The XCHD instruction swaps the low nibble of the accumulator with the > low nibble of @R0 or @R1. My guess is that this instruction was included > to marginally "optimize" packing/unpacking two BCD or HEX digits in/from > a byte - for instance in a calculator. > > The specificity of the XCHD instructions (and a few others) makes me > suspect that it is unlikely that they are produced by a C compiler[*], > though they may be used in handcrafted assembly library routines. If I > were to venture a guess, I would also expect that the SWAP, DA, NOP > instructions will not be produced by a C compiler (and perhaps also not > the RR,RL, RRC and RLC instructions) > > regards, Theo > >
Sorry, yes, I confused xchd with xch. Then xchd is similar to Z80 rrd / rld, I guess. SDCC sometimes uses those in the z80 backend, mostly for packing / unpacking of 4-bit bitfields. Philipp _______________________________________________ Sdcc-user mailing list Sdcc-user@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sdcc-user
