Re: [PATCH qemu 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

ructions, any element in the tail of the result can be written with the value the mask-producing operation would have calculated with vl=VLEN, SEW=8, and LMUL=8 (i.e., all bits of the mask register can be overwritten)." Regards, Weiwei Li GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_M

Re: [PATCH qemu 03/13] target/riscv: rvv: Early exit when vstart >= vl

ess require vstart to be zero. so these checks seem  unnecessary. Regards, Weiwei Li

Re: [PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions

在 2022/3/21 下午3:50, eop Chen 写道: Hi WeiWei, Thanks for reviewing this PR. === Regarding to possible behaviors on agnostic elements to mask instructions, I want to ask for you and other's opinion on this propos

Re: [PATCH qemu v3 03/14] target/riscv: rvv: Early exit when vstart >= vl

_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); vmsbf.m, vmsif.m,vmsof.m, viota.m, vcompress instructions themselves require vstart to be zero. So it seems unnecessary here.  By the way, I remember I have commented this in last patchset. We both lost it in our previous discussion.

Re: [PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

vext_vv(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc, - opivv2_fn *fn) + opivv2_fn *fn, uint32_t esz) { uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; +uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); 'vlmax' seems a bit confusing here. Maybe can use 'total' or 'max' ... Regards, Weiwei Li

Re: [PATCH qemu v3 00/14] Add tail agnostic behavior for rvv instructions

ostic elements to all 1s makes things simple and allow QEMU to express this. We may explore other possibility of agnostic behavior by adding other options in the future. Please understand that this patch-set is limited. v2 updates: - Addressed comments from Weiwei Li - Added commit tail agnostic on lo

Re: [RFC PATCH v2 2/4] target/riscv: smstateen check for h/senvcfg

ONE; +} + +if (!(env->mstateen[0] & 1UL << bit)) { +return RISCV_EXCP_ILLEGAL_INST; +} I think here should be " & (1UL << bit) " . The same for following similar cases. Regards, Weiwei Li

Re: [RFC PATCH v2 1/4] target/riscv: Add smstateen support

+ .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver = PRIV_VERSION_1_12_0

Re: [RFC PATCH v2 4/4] target/riscv: smstateen check for AIA/IMSIC

L << SMSTATEEN0_AIA) +| (1UL << SMSTATEEN0_SVSLCT); I think it's better as follows: +wr_mask |= (1UL << SMSTATEEN0_IMSIC) | + (1UL << SMSTATEEN0_AIA) | + (1UL << SMSTATEEN0_SVSLCT); Regards, Weiwei Li

Re: [PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

在 2022/3/23 下午3:30, 陳約廷 写道: How about ‘total_elem'? LGTM. Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年3月23日 下午3:28 寫道： 在 2022/3/1 下午5:07, ~eopxd 写道: From: eopXD mailto:eop.c...@sifive.com>> This is the first commit regarding the tail agnostic behavior. Added opti

[PATCH 2/2] target/riscv: optimize helper for vmvr.v

LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share the same helper Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/helper.h | 5 + target/riscv/insn_trans/trans_rvv.c.inc | 17 +-- target/riscv/vector_helper.c

[PATCH 1/2] target/riscv: optimize condition assign for scale < 0

for some cases, scale is always equal or less than 0, since lmul is not larger than 3 Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvv.c.inc | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans

Re: [PATCH qemu v4 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

hset to  try to optimize a few point for rvv.  One of the point I haven't done is that, for some rvv instructions, lmul field in 'desc'( or the total desc) is assigned in trans_* but not used in helper function. This field seems can be used here. I think It may be better to use desc and esz(just like vext_max_elems) here. Regards, Weiwei Li

Re: [PATCH qemu v4 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

* set tail elements to 1s + */ It seems better to as follows: +/* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ Regards, Weiwei Li

Re: [PATCH qemu v4 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

\ }\ env->vstart = 0; \ +/* set tail elements to 1s */\ +vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \ + total_elems * esz); \ } GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1) Regards, Weiwei Li

Re: [PATCH qemu v4 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ +uint32_t total_elems = \ +vext_get_total_elems(env_archcpu(env), \ +env->vtype); \ It's  better to aligned here too. Regards, Weiwei Li

Re: [PATCH qemu v4 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions

esc); uint32_t vl = env->vl; +uint32_t esz = sizeof(uint32_t); +uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3; vlenb  also can get from maxsz field of desc,  that is uint32_tvlenb= simd_maxsz(desc) Regards, Weiwei Li

Re: [PATCH qemu v4 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions

ELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ -uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2))); \ +uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(TS2))); \ similar to above. Regards, Weiwei Li

Re: [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions

, uint32_t esz) +{ +uint32_t vlenb = simd_maxsz(desc); +int8_t lmul = vext_lmul(desc) < 0 ? 0 : vext_lmul(desc); + +return vlenb >> (esz - lmul); +} + seems incorrect here. if esz is used here, I think the max elements should be:     (vlenb << lmul) / esz; otherwise, if take the similar way as vext_max_elems, log2_esz is used, the max element can be: int scale = lmul - log2_esz; return scale < 0 ? vlenb >> -scale : vlenb << scale; Regards, Weiwei Li

Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

Or LMUL should be equal or greater than 1 here? I didn't find any description about this from the spec. I also have another question about the tail elements for these load/store instructions: when nf = 3, LMUL = 1, vl=vlmax,  reg, reg+1, reg+2 will be loaded, then whether elements in reg+3 (if they belong to the same register group) are tail elements? Regards, Weiwei Li

[PATCH] target/riscv: fix start byte for vmvr.v when vstart != 0

The spec for vmvr.v says: 'the instructions operate as if EEW=SEW, EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' So the start byte for vstart != 0 should take sew into account Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/vector_helper.c | 8 +-

[RESEND PATCH] target/riscv: fix start byte for vmvr.v when vstart != 0

The spec for vmvr.v says: 'the instructions operate as if EEW=SEW, EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' So the start byte for vstart != 0 should take sew into account Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/vector_helper.c | 8 +-

Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

在 2022/3/30 下午3:42, 陳約廷 写道: Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年3月28日 下午7:56 寫道： 在 2022/3/7 下午3:10, ~eopxd 写道: From: eopXD mailto:eop.c...@sifive.com>> Signed-off-by: eop Chen <mailto:eop.c...@sifive.com>> Reviewed-by: Frank Chang <mailto:frank.ch...@s

Re: [PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions

ostic elements to all 1s makes things simple and allow QEMU to express this. We may explore other possibility of agnostic behavior by adding other options in the future. Please understand that this patch-set is limited. v2 updates: - Addressed comments from Weiwei Li - Added commit tail agnostic on lo

Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

在 2022/3/30 下午6:02, eop Chen 写道: Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年3月30日 下午4:27 寫道： 在 2022/3/30 下午3:42, 陳約廷 写道: Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年3月28日 下午7:56 寫道： 在 2022/3/7 下午3:10, ~eopxd 写道: From: eopXD mailto:eop.c...@sifive.com>>

Re: [PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions

在 2022/3/31 上午8:11, Alistair Francis 写道: On Wed, Mar 30, 2022 at 10:52 PM Weiwei Li wrote: 在 2022/3/30 下午6:24, ~eopxd 写道: According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies,

Re: [PATCH v9 12/14] target/riscv: rvk: add CSR support for Zkr

/archive/html/qemu-riscv/2022-03/msg00156.html) Regards, Weiwei Li 在 2022/3/18 下午12:19, Weiwei Li 写道: - add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction

Re: [PATCH v9 12/14] target/riscv: rvk: add CSR support for Zkr

Thanks for your comments. 在 2022/4/14 上午7:57, Alistair Francis 写道: On Mon, Apr 11, 2022 at 2:46 PM Weiwei Li wrote: Hi, any comments on this patch or patchset? Currently, read-only instruction to access Seed CSR is checked as a special case in helper_csrr as suggested in https

[PATCH v10 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index faa41217d2..365bdd5fe5

[PATCH v10 00/14] support subsets of scalar crypto extension

ip * use aes related sbox array from crypto/aes.h * move sm4_sbox to crypto/sm4.c, and share it with target/arm Weiwei Li (14): target/riscv: rvk: add cfg properties for zbk* and zk* target/riscv: rvk: add support for zbkb extension target/riscv: rvk: add support for zbkc extension target/riscv:

[PATCH v10 02/14] target/riscv: rvk: add support for zbkb extension

- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c

[PATCH v10 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans

[PATCH v10 04/14] target/riscv: rvk: add support for zbkx extension

- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/bitmanip_helper.c | 27 + target/riscv/helper.h | 2 ++ target/riscv

[PATCH v10 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans

[PATCH v10 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 105 target

[PATCH v10 03/14] target/riscv: rvk: add support for zbkc extension

- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvb.c.inc | 4

[PATCH v10 05/14] crypto: move sm4_sbox from target/arm

- share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- crypto/meson.build | 1 + crypto/sm4.c | 49

[PATCH v10 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- disas/riscv.c | 173 +- 1 file changed, 172 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b

[PATCH v10 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6

[PATCH v10 11/14] target/riscv: rvk: add support for zksed/zksh extension

- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 28 target/riscv/helper.h

[PATCH v10 12/14] target/riscv: rvk: add CSR support for Zkr

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_bits.h | 9 + target/riscv/csr.c | 80 target/riscv/op_helper.c | 9 + target/riscv/pmp.h | 8 ++-- 4 files changed, 103 insertions(+), 3 deletions(-) diff

[PATCH v10 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/crypto_helper.c

[PATCH v10 14/14] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 365bdd5fe5..973dd5ea47 100644 --- a/target/riscv/cpu.c +++ b/target/riscv

[PATCH v11 04/14] target/riscv: rvk: add support for zbkx extension

- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/bitmanip_helper.c | 27 + target/riscv/helper.h | 2 ++ target/riscv

[PATCH v11 02/14] target/riscv: rvk: add support for zbkb extension

- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c

[PATCH v11 03/14] target/riscv: rvk: add support for zbkc extension

- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvb.c.inc | 4

[PATCH v11 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/crypto_helper.c

[PATCH v11 11/14] target/riscv: rvk: add support for zksed/zksh extension

- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 28 target/riscv/helper.h

[PATCH v11 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans

[PATCH v11 05/14] crypto: move sm4_sbox from target/arm

- share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- crypto/meson.build | 1 + crypto/sm4.c | 49

[PATCH v11 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index faa41217d2..365bdd5fe5

[PATCH v11 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 105 target

[PATCH v11 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6

[PATCH v11 00/14] support subsets of scalar crypto extension

atches v4: * drop "x-" in exposed properties * delete unrelated changes v3: * add extension check for SEED csr access v2: * optimize implementation for brev8, xperm, zip, unzip * use aes related sbox array from crypto/aes.h * move sm4_sbox to crypto/sm4.c, and share it with target/arm

[PATCH v11 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- disas/riscv.c | 173 +- 1 file changed, 172 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b

[PATCH v11 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans

[PATCH v11 14/14] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 365bdd5fe5..973dd5ea47 100644 --- a/target/riscv/cpu.c +++ b/target/riscv

[PATCH v11 12/14] target/riscv: rvk: add CSR support for Zkr

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_bits.h | 9 + target/riscv/csr.c | 80 target/riscv/op_helper.c | 9 + target/riscv/pmp.h | 8 ++-- 4 files changed, 103 insertions(+), 3 deletions(-) diff

[PATCH v12 04/14] target/riscv: rvk: add support for zbkx extension

- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/bitmanip_helper.c | 27 + target/riscv/helper.h | 2 ++ target/riscv

[PATCH v12 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ace68ed855..62a47c197b

[PATCH v12 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6

[PATCH v12 00/14] support subsets of scalar crypto extension

/sm4.c, and share it with target/arm Weiwei Li (14): target/riscv: rvk: add cfg properties for zbk* and zk* target/riscv: rvk: add support for zbkb extension target/riscv: rvk: add support for zbkc extension target/riscv: rvk: add support for zbkx extension crypto: move sm4_sbox from

[PATCH v12 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 105 target

[PATCH v12 02/14] target/riscv: rvk: add support for zbkb extension

- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c

[PATCH v12 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/crypto_helper.c

[PATCH v12 03/14] target/riscv: rvk: add support for zbkc extension

- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvb.c.inc | 4

[PATCH v12 12/14] target/riscv: rvk: add CSR support for Zkr

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 9 + target/riscv/csr.c | 80 target/riscv/op_helper.c | 9 + target/riscv/pmp.h | 8 ++-- 4 files changed, 103

[PATCH v12 05/14] crypto: move sm4_sbox from target/arm

- share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- crypto/meson.build | 1 + crypto/sm4.c | 49

[PATCH v12 14/14] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 62a47c197b..dff4606585 100644 --- a/target/riscv/cpu.c +++ b/target/riscv

[PATCH v12 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans

[PATCH v12 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- disas/riscv.c | 173 +- 1 file changed, 172 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b

[PATCH v12 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans

[PATCH v12 11/14] target/riscv: rvk: add support for zksed/zksh extension

- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/crypto_helper.c| 28 target/riscv/helper.h

Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions

t discussion,  vext_set_elems_1s_fns array can be simplified to single vext_set_elems_1s, since the fourth argement can be used as the start offset. Another question, may be not related to this patchset, in section 3.4.3 of the spec: /"Mask destination tail elements are always treated

[PATCH] target/riscv: add scalar crypto related extenstion strings to isa_string

- add zbk* and zk* strings to isa_edata_arr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dff4606585..ccacdee215 100644 --- a/target/riscv/cpu.c

Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions

在 2022/4/27 上午2:20, eop Chen 写道: Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年4月26日 下午4:47 寫道： 在 2022/3/17 下午3:26, ~eopxd 写道: From: Yueh-Ting (eop) Chen This is the first commit regarding the mask agnostic behavior. Added option 'rvv_ma_all_1s' to enable the behavio

Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions

在 2022/4/27 上午10:07, eop Chen 写道: 在 2022/4/27 上午2:20, eop Chen 写道: Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年4月26日 下午4:47 寫道： 在 2022/3/17 下午3:26, ~eopxd 写道: From: Yueh-Ting (eop) Chen This is the first commit regarding the mask agnostic behavior. Added option 'rvv_ma

[PATCH] target/riscv: Update CSR bits name for svadu extension

The Svadu specification updated the name of the *envcfg bit from HADE to ADUE. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c| 4 ++-- target/riscv/cpu_bits.h | 8 target/riscv/cpu_helper.c | 4 ++-- target/riscv/csr.c| 12

[PATCH v2] target/riscv: Update CSR bits name for svadu extension

The Svadu specification updated the name of the *envcfg bit from HADE to ADUE. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- v2: * rename hade variable name to adue suggested by Daniel target/riscv/cpu.c| 4 ++-- target/riscv/cpu_bits.h | 8 target/riscv

Re: [PATCH] target/riscv: Fix LMUL check to use minimum SEW

pec in another way: we must support lmul=1/8 when ELEN=64, but it's only available when sew = 8. Regards, Weiwei Li ` Regards, Weiwei Li Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") Signed-off-by: Rob Bradford --- target/riscv/vector_helper.c |

Re: [PATCH for-8.2 v3 5/8] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro

On 2023/7/15 01:43, Daniel Henrique Barboza wrote: The code inside riscv_cpu_add_user_properties() became quite repetitive after recent changes. Add a macro to hide the repetition away. Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c

Re: [PATCH for-8.2 v3 6/8] target/riscv: add 'max' CPU type

disabled. This is the resulting 'riscv,isa' DT for this new CPU: rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_ zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_ zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_ smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt Signed-off-by: Daniel Henrique Barboza --- R

Re: [PATCH] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

("target/riscv: add cfg properties for Zc* extension") Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..6b93

Re: [PATCH] target/riscv: Fix LMUL check to use minimum SEW

On 2023/7/17 23:13, Rob Bradford wrote: On Thu, 2023-07-06 at 21:22 +0800, Weiwei Li wrote: On 2023/7/6 18:44, Rob Bradford wrote: The previous check was failing with: ELEN = 64 SEW = 16 and LMUL = 1/8 (encoded as 5) which is a valid combination. Fix the check to correctly match the

Re: [PATCH 1/2] target/riscv: Remove redundant check in pmp_is_locked

On 2023/6/28 18:36, Ruibo Lu wrote: the check of top PMP is redundant and will not influence the return value, so consider remove it Signed-off-by: Ruibo Lu --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/pmp.c | 5 - 1 file changed, 5 deletions(-) diff --git a/target/riscv

Re: [PATCH 2/2] target/riscv: Optimize ambiguous local variable in pmp_hart_has_privs

a_field)) { +if ((sa_in & ea_in) && (PMP_AMATCH_OFF != a_field)) { I think it's better to use "sa_in && ea_in &&(...)" here. Regards, Weiwei Li /* * If the PMP entry is not off and the address is in range, * do the priv check

[PATCH v3 0/1] target/riscv: Add support for BF16 extensions

extensions in patch 1 and patch 4 * Update encodings for BF16 instructions in patch 2,3,4 * Add disas support for BF16 instructions in patch 6 Weiwei Li (1): target/riscv: Add disas support for BF16 extensions disas/riscv.c | 44 1 file changed, 44

[PATCH v3 1/1] target/riscv: Add disas support for BF16 extensions

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 44 1 file changed, 44 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 94e568a7e9..9f0195be30 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -819,6 +819,16

[PATCH] target/riscv: Fix initialized value for cur_pmmask

. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 09ea227ceb..acbcb7ed76 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv

Re: [PATCH 1/4] target/riscv: Make MPV only work when MPP != PRV_M

On 2023/6/12 10:45, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: Upon MRET or explicit memory access with MPRV=1, MPV should be ignored when MPP=PRV_M. Does MPP==PRV_M always indicate the MPV==0? No, I think . The spec doesn't restrict this. When MPP=PRV_M, MPV wll be

Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

On 2023/6/12 11:08, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: MPV and GVA bits are added by hypervisor extension to mstatus and mstatush (if MXLEN=32). Have you found the CSR field specifications for them, especially for GVA. Yeah.  in the section 9.4.1 of the privilege spec

Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

On 2023/6/12 11:18, LIU Zhiwei wrote: On 2023/6/12 11:16, Weiwei Li wrote: On 2023/6/12 11:08, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: MPV and GVA bits are added by hypervisor extension to mstatus and mstatush (if MXLEN=32). Have you found the CSR field specifications

Re: [PATCH 3/4] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled

On 2023/6/12 13:40, LIU Zhiwei wrote: On 2023/6/12 12:35, Weiwei Li wrote: On 2023/6/12 11:18, LIU Zhiwei wrote: On 2023/6/12 11:16, Weiwei Li wrote: On 2023/6/12 11:08, LIU Zhiwei wrote: On 2023/5/29 20:17, Weiwei Li wrote: MPV and GVA bits are added by hypervisor extension to

[PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV

Pointer mask is also affected by MPRV which means cur_pmbase/pmmask should also take MPRV into consideration. As pointer mask for instruction is not supported currently, so we can directly update cur_pmbase/pmmask based on address related mode and xlen affected by MPRV now. Signed-off-by: Weiwei

[PATCH 1/2] target/riscv: Add additional xlen for address when MPRV=1

As specified in privilege spec:"When MPRV=1, load and store memory addresses are treated as though the current XLEN were set to MPP’s XLEN". So the xlen for address may be different from current xlen. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h

[PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1

Currently, we use the current env->xl as the xlen for address. However, the xlen for data address should be changed to the xlen related to MPP when MPRV=1. The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-addr-xl-upstream Weiwei Li (2): target/riscv: Add additio

[PATCH v2 5/6] target/riscv: Expose properties for BF16 extensions

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dc6b2f72f6..feb0ee5e6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv

[PATCH v2 1/6] target/riscv: Add properties for BF16 extensions

Add ext_zfbfmin/zvfbfmin/zvfbfwma properties. Add require check for BF16 extensions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 20 target/riscv/cpu_cfg.h | 3 +++ 2 files changed, 23 insertions

[PATCH v2 0/6] target/riscv: Add support for BF16 extensions

in patch 2,3,4 * Add disas support for BF16 instructions in patch 6 Weiwei Li (6): target/riscv: Add properties for BF16 extensions target/riscv: Add support for Zfbfmin extension target/riscv: Add support for Zvfbfmin extension target/riscv: Add support for Zvfbfwma extension target

[PATCH v2 4/6] target/riscv: Add support for Zvfbfwma extension

Add trans_* and helper function for Zvfbfwma instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvbf16

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