Re: [PATCH qemu v4 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

[Weiwei Li]

在 2022/3/7 下午3:32, ~eopxd 写道:

From: eopXD <eop.c...@sifive.com>

Signed-off-by: eop Chen <eop.c...@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
---
  target/riscv/insn_trans/trans_rvv.c.inc |  23 ++
  target/riscv/vector_helper.c            | 312 +++++++++++++-----------
  2 files changed, 197 insertions(+), 138 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index fee616ef38..e8ef5b1e0e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1296,6 +1296,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, 
uint32_t vs2, uint32_t vm,

data = FIELD_DP32(data, VDATA, VM, vm);

      data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
      desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
                                        s->cfg_ptr->vlen / 8, data));

@@ -1332,6 +1333,15 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,

      }

if (a->vm && s->vl_eq_vlmax) {

+        if (s->vta && s->lmul < 0) {
+            /* tail elements may pass vlmax when lmul < 0
+             * set tail elements to 1s
+             */

It seems better to as follows:

+            /*
+             * tail elements may pass vlmax when lmul < 0
+             * set tail elements to 1s
+             */
Regards,
Weiwei Li