[PATCH v7 4/5] target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target

[PATCH v7 0/5] support subsets of virtual memory extension

o describe changes v3: * drop "x-" in exposed properties v2: * add extension check for svnapot and svpbmt Guo Ren (1): target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support f

[PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv

[PATCH v7 5/5] target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/

[PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual

[PATCH v5 3/6] target/riscv: add support for zfinx

- update extension check REQUIRE_ZFINX_OR_F - update single float point register read/write - disable nanbox_s check Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 89

[PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}

Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 12 target/riscv/cpu.h | 4 target/riscv/translate.c | 8 3 files changed, 24 insertions

[PATCH v5 5/6] target/riscv: add support for zhinx/zhinxmin

- update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN - update half float point register read/write - disable nanbox_h check Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c

[PATCH v5 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties

Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7006e6647b..e96d0a73f5

[PATCH v5 4/6] target/riscv: add support for zdinx

-- update extension check REQUIRE_ZDINX_OR_D -- update double float point register read/write Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.c.inc | 285 +--- target

[PATCH v5 0/6] support subsets of Float-Point in Integer Registers extensions

tial implemention as suggested Weiwei Li (6): target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add support for zfinx target/riscv: add support for zdinx target/riscv: add support for zhinx/zhinxmin target

[PATCH v5 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx

Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +- target/riscv/csr.c| 25 - target/riscv/translate.c | 4 3 files changed, 29 insertions(+), 6 deletions

Re: [PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64

在 2022/2/1 上午11:31, Alistair Francis 写道: On Fri, Jan 28, 2022 at 7:11 PM Weiwei Li wrote: From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged

Re: [PATCH v7 3/5] target/riscv: add support for svnapot extension

在 2022/2/1 下午2:22, Alistair Francis 写道: On Fri, Jan 28, 2022 at 6:57 PM Weiwei Li wrote: - add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by

[PATCH v8 0/5] support subsets of virtual memory extension

heck for svnapot and svpbmt Guo Ren (1): target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: ad

[PATCH v8 5/5] target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/

[PATCH v8 1/5] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual

[PATCH v8 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv

[PATCH v8 4/5] target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target

[PATCH v8 3/5] target/riscv: add support for svnapot extension

- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu.c| 2 ++ target/riscv/cpu_bits.h | 1 + target

Re: [PATCH v8 3/5] target/riscv: add support for svnapot extension

在 2022/2/3 上午6:25, Alistair Francis 写道: On Wed, Feb 2, 2022 at 3:24 AM Weiwei Li wrote: - add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by

[PATCH v9 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv

[PATCH v9 3/5] target/riscv: add support for svnapot extension

- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 2 ++ target/riscv

[PATCH v9 5/5] target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Ali

[PATCH v9 4/5] target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by

[PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual

[PATCH v9 0/5] support subsets of virtual memory extension

posed properties v2: * add extension check for svnapot and svpbmt Guo Ren (1): target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/riscv: add support for svinva

Re: [PATCH v2 5/6] target/riscv: Add *envcfg* CSRs support

eption write_menvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ +uint64_t valh = (uint64_t)val << 32; +env->menvcfg |= valh; + The original high32 of menvcfg should be cleared before ' | ' valh. Similar for henvcfgh. Regards,

Re: [PATCH v2 4/6] target/riscv: Add support for mconfigptr

s, write_mstatus, NULL, Additional spaces before '=' seems to align with other '='s in near lines. If you don't want to modify the previous lines, I think  it's better to align with the '=' of CSR_MSTATUS  or  doesn't add any additional spaces. Regards, Weiwei Li

Re: [PATCH v3 2/3] target/riscv: add support for svinval extension

Thanks for your comments. 在 2022/1/14 下午9:40, Anup Patel 写道: On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote: Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv

Re: [PATCH v3 2/3] target/riscv: add support for svinval extension

在 2022/1/14 下午10:01, Anup Patel 写道: On Fri, Jan 14, 2022 at 7:24 PM Weiwei Li wrote: Thanks for your comments. 在 2022/1/14 下午9:40, Anup Patel 写道: On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote: Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c

Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension

在 2022/1/14 下午9:59, Anup Patel 写道: On Fri, Jan 14, 2022 at 7:11 AM Weiwei Li wrote: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Tested-by:

[PATCH v4 3/4] target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target

[PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 434a83e66a..d84cde424d 100644 --- a/target/riscv/cpu_helper.c +++ b

[PATCH v4 2/4] target/riscv: add support for svnapot extension

- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c| 2 ++ target/riscv/cpu.h| 1 + target/riscv/cpu_bits.h | 1

[PATCH v4 0/4] support subsets of virtual memory extension

nd fourth commits * improve commit messages to describe changes v3: * drop "x-" in exposed properties v2: * add extension check for svnapot and svpbmt Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/ri

[PATCH v4 4/4] target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bits check for inner PTE - add reserved bits check for all PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Test

Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension

在 2022/1/17 下午3:18, Guo Ren 写道: On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li wrote: - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bits check for inner PTE - add res

Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto

在 2022/1/18 上午7:28, Alistair Francis 写道: On Tue, Jan 11, 2022 at 1:57 PM Weiwei Li wrote: - share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Do you mind fixing up the commit title? Maybe something

[PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 26608ddf1c..1820188f41 100644 --- a/target/riscv/cpu_helper.c +++ b

[PATCH v5 0/5] support subsets of virtual memory extension

rved bits in PTE for RV64 Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: add support for svpbmt extension target/riscv/cpu.c |

[PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual

[PATCH v5 5/5] target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Heiko Stuebner Cc: Anup Patel --- t

[PATCH v5 3/5] target/riscv: add support for svnapot extension

- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Anup Patel --- target/riscv/cpu.c| 2 ++ target/riscv/cpu.h| 1 + target/riscv

[PATCH v5 4/5] target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target

Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties

在 2022/1/18 下午12:23, Alistair Francis 写道: On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li wrote: Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*

在 2022/1/18 下午12:40, Alistair Francis 写道: On Tue, Jan 11, 2022 at 1:56 PM Weiwei Li wrote: - reuse partial instructions of Zbb/Zbc extensions - add brev8, packh, unzip, zip, etc. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/bitmanip_helper.c

Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr

在 2022/1/18 下午12:36, Alistair Francis 写道: On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li wrote: - add SEED CSR - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv

Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*

在 2022/1/18 下午12:21, Alistair Francis 写道: On Tue, Jan 11, 2022 at 2:01 PM Weiwei Li wrote: Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/crypto_helper.c| 446 ++ target/riscv

Re: [PATCH v4 0/7] support subsets of scalar crypto extension

在 2022/1/18 下午12:41, Alistair Francis 写道: On Tue, Jan 11, 2022 at 1:54 PM Weiwei Li wrote: This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions. Partial instructions are reused from B-extension. Specification: https://github.com/riscv/riscv-crypto The port

Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension

在 2022/1/18 上午11:32, Anup Patel 写道: On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: - add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Anup Patel

Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension

在 2022/1/18 上午11:35, Anup Patel 写道: On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-o

Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension

在 2022/1/18 上午11:35, Anup Patel 写道: On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-o

Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension

在 2022/1/18 下午7:04, Anup Patel 写道: On Tue, Jan 18, 2022 at 2:40 PM Weiwei Li wrote: 在 2022/1/18 上午11:35, Anup Patel 写道: On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent

Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64

在 2022/1/18 下午7:15, Guo Ren 写道: On Tue, Jan 18, 2022 at 4:51 PM Anup Patel wrote: On Tue, Jan 18, 2022 at 2:16 PM Guo Ren wrote: On Tue, Jan 18, 2022 at 11:32 AM Anup Patel wrote: On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote: From: Guo Ren Highest bits of PTE has been used for

[RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension

- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvb.c.inc | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff

[RFC PATCH v5 04/14] target/riscv: rvk: add support for zbkx extension

- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/bitmanip_helper.c | 27 + target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 target/riscv/insn_trans

[RFC PATCH v5 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9bc25d3055..b487a8282c

[RFC PATCH v5 00/14] support subsets of scalar crypto extension

p * use aes related sbox array from crypto/aes.h * move sm4_sbox to crypto/sm4.c, and share it with target/arm Weiwei Li (14): target/riscv: rvk: add cfg properties for zbk* and zk* target/riscv: rvk: add support for zbkb extension target/riscv: rvk: add support for zbkc extension target/ri

[RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension

- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/bitmanip_helper.c | 53 +++ target/riscv/helper.h

[RFC PATCH v5 05/14] crypto: move sm4_sbox from target/arm

- share it between target/arm and target/riscv Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- crypto/meson.build | 1 + crypto/sm4.c | 49 ++ include

[RFC PATCH v5 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32

- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/crypto_helper.c| 139 target/riscv/helper.h | 6 + target/riscv/insn32

[RFC PATCH v5 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/crypto_helper.c| 57 target/riscv/helper.h | 7

[RFC PATCH v5 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension

- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/crypto_helper.c| 31 + target/riscv/helper.h | 5 +++ target/riscv/insn32.decode

[RFC PATCH v5 11/14] target/riscv: rvk: add support for zksed/zksh extension

- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/crypto_helper.c| 49 + target/riscv/helper.h | 6 +++ target/riscv/insn32.decode | 6

[RFC PATCH v5 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/crypto_helper.c| 136 target/riscv/helper.h

[RFC PATCH v5 12/14] target/riscv: rvk: add CSR support for Zkr

- add SEED CSR - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu_bits.h | 9 ++ target/riscv/csr.c | 64 + target/riscv

[RFC PATCH v5 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/crypto_helper.c| 31 ++ target/riscv/helper.h | 5 +++ target/riscv/insn32.decode

[RFC PATCH v5 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Co-authored-by: Ruibo Lu Co-authored-by: Zewen Ye Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 170 ++ 1 file changed, 170 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 03c8dc9961..44a2c16a0b 100644

[RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b487a8282c..04e8e8d3c6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -694,7 +694,20

Re: [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties

在 2022/1/21 上午8:35, Alistair Francis 写道: On Wed, Jan 19, 2022 at 11:09 PM Weiwei Li wrote: Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair Thanks for your comments. Regards, Weiwei Li --- target/riscv/cpu.c | 13 + 1 file

[PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual

[PATCH v6 0/5] support subsets of virtual memory extension

(1): target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: add support for svpbmt extension

[PATCH v6 3/5] target/riscv: add support for svnapot extension

- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu.c| 2 ++ target/riscv/cpu_bits.h | 1 + target

[PATCH v6 4/5] target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target

[PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2a921bedfd..a5bf07ccb6 100644 --- a/target/riscv/cpu_helper.c +++ b

[PATCH v6 5/5] target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel --- target/riscv/

Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

在 2022/1/25 下午5:00, Guo Ren 写道: On Tue, Jan 25, 2022 at 4:54 PM LIU Zhiwei wrote: On 2022/1/25 16:40, Guo Ren wrote: On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei wrote: On 2022/1/25 14:45, Weiwei Li wrote: From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we

Re: [PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions

re. +if (ret == TLB_INVALID_MASK) { +uint32_t exc = RISCV_EXCP_STORE_PAGE_FAULT; + +#ifndef CONFIG_USER_ONLY +/* User-mode emulation does not have virtualisation... */ +if (riscv_cpu_virt_enabled(env)) { + exc = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; +} +

Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support

_UINTTL(env.senvcfg, RISCVCPU), +VMSTATE_UINTTL(env.henvcfg, RISCVCPU), +VMSTATE_UINTTL(env.henvcfgh, RISCVCPU), + +VMSTATE_END_OF_LIST() +} +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, @@ -240,6 +265,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_vector, &vmstate_pointermasking, &vmstate_rv128, +&vmstate_envcfg, NULL } }; Regards, Weiwei Li

Re: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault

It seems that target is miswritten to "targett"  in commit message. Regards, Weiwei Li 在 2022/1/24 上午8:59, Alistair Francis 写道: From: Alistair Francis If the atomic operation fails we want to generate a MMU_DATA_STORE access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAU

Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

;& !vext_elem_mask(v0, i)) { -continue; -} - k = 0; while (k < nf) { +if (!vm && !vext_elem_mask(v0, i)) { +/* set masked-off elements to 1s */ +vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz, seems lack a space here. the same to following cases. Regards, Weiwei Li

Re: [PATCH qemu v2 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

get/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/internals.h| 5 +++-- target/riscv/translate.c| 2 ++ target/riscv/vector_helper.c| 8 6 files changed, 20 insertions(+), 2 deletions(-) Reviewed-by: Weiwei Li Regards, Weiwei Li diff

Re: [PATCH qemu v2 03/10] target/riscv: rvv: Add mask agnostic for vx instructions

在 2022/3/17 下午4:38, ~eopxd 写道: From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c| 3 +++ 2 files changed, 5 insertions(+) Reviewed-by: Weiwei Li Regards, Weiwei Li

Re: [PATCH qemu v2 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions

在 2022/3/17 下午4:43, ~eopxd 写道: From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 7 +++ 2 files changed, 8 insertions(+) Reviewed-by: Weiwei Li Regards, Weiwei

Re: [PATCH qemu v2 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions

在 2022/3/17 下午4:46, ~eopxd 写道: From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 10 ++ 2 files changed, 11 insertions(+) Reviewed-by: Weiwei Li Regards

Re: [PATCH qemu v2 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions

在 2022/3/17 下午4:52, ~eopxd 写道: From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/vector_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) Reviewed-by: Weiwei Li Regards, Weiwei Li diff --git a

Re: [PATCH qemu v2 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions

(+) Reviewed-by: Weiwei Li Regards, Weiwei Li diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5cbf323c18..8fb8045957 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2428,6 +2428,7 @@ static bool

Re: [PATCH qemu v2 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions

在 2022/3/17 下午5:14, ~eopxd 写道: From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 14 insertions(+) Reviewed-by: Weiwei Li

Re: [PATCH qemu v2 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior

vv_ma_all_1s' is added to enable the behavior, it is default as disabled. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Weiwei Li Regards, Weiwei Li diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

Re: [PATCH qemu v2 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions

(-) Reviewed-by: Weiwei Li Regards, Weiwei Li diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 18ef9949ad..d853f9f2c4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3988,6 +3988,7 @@ static bool

Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

(i + k * max_elems + 1) * esz); +k++; +continue; There is another question here: this function is reused by load&store. However  vd is used as source for store. So we cannot set it without distinguish load and s

Re: [PATCH qemu v16 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions

ast register should be treated as tail elements. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 11 + target/riscv/translate.c| 2 + target/riscv/vector_helper.c|

Re: [PATCH qemu v3 00/10] Add mask agnostic behavior for rvv instructions

d missing space - Trigger `vma` when encountering vector load instructions and not in vector stores Instead of add is_load in the helper functions, maybe it's better to just not set vta and vma for vector store instructions in trans_rvv. Regards, Weiwei Li Yueh-Ting (eop) Chen (9): ta

Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

(-) Reviewed-by: Weiwei Li Regards, Weiwei Li diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index df5a892150..a6daf20714 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -712,6 +712,7 @@ static

Re: [PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

在 2022/5/14 上午12:09, Weiwei Li 写道: 在 2022/3/17 下午3:47, ~eopxd 写道: From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang ---   target/riscv/insn_trans/trans_rvv.c.inc |  5   target/riscv/vector_helper.c    | 35 +   2 files changed

Re: [PATCH v2 4/5] target/riscv: FP extension requirements

requires D Why 'V requires D'? I know partial vector instructions require D, However,  I think they  just like c.fsd instruction requires D, not 'C requires D' or 'D requires C'. Is there any rvv spec change I don't know? Regards. Weiwei Li Because F/D/Z

Re: [PATCH v2 4/5] target/riscv: FP extension requirements

在 2022/5/15 下午10:45, Tsukasa OI 写道: On 2022/05/15 23:37, Weiwei Li wrote: 在 2022/5/15 上午10:56, Tsukasa OI 写道: QEMU allowed inconsistent configurations that made floating point arithmetic effectively unusable. This commit adds certain checks for consistent FP arithmetic: -   F requires

Re: [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks

rectly by cfg property, such as we can set cpu option to sifive-u34 with zfinx=true. This may not be a proper way to set cpu option, However it's truly a legal command option, but  configure an illegal supported ISA which enable both f and zfinx. Regards, Weiwei Li if (cpu-

[PATCH 2/2] target/riscv: disable zb* extensions by default

- enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target

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