Re: [PATCH v8 3/5] target/riscv: add support for svnapot extension

[Weiwei Li]

在 2022/2/3 上午6:25, Alistair Francis 写道:
On Wed, Feb 2, 2022 at 3:24 AM Weiwei Li <liwei...@iscas.ac.cn> wrote:
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)

Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
Reviewed-by: Anup Patel <a...@brainfault.org>
---
  target/riscv/cpu.c        |  2 ++
  target/riscv/cpu_bits.h   |  1 +
  target/riscv/cpu_helper.c | 18 +++++++++++++++---
  3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6df07b8289..cfaccdfc72 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,6 +729,8 @@ static Property riscv_cpu_properties[] = {
      DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
      DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),

+    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+
      DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
      DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
      DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6ea3944423..7abe9607ff 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -489,6 +489,7 @@ typedef enum {
  #define PTE_A               0x040 /* Accessed */
  #define PTE_D               0x080 /* Dirty */
  #define PTE_SOFT            0x300 /* Reserved for Software */
+#define PTE_N               0x8000000000000000ULL /* NAPOT translation */

  /* Page table PPN shift amount */
  #define PTE_PPN_SHIFT       10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 61c3a9a4ad..77b263c37e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -456,6 +456,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr 
*physical,
      bool use_background = false;
      hwaddr ppn;
      RISCVCPU *cpu = env_archcpu(env);
+    int napot_bits = 0;
+    target_ulong napot_mask;

      /*
       * Check if we should use the background registers for the two
@@ -640,7 +642,7 @@ restart:
              return TRANSLATE_FAIL;
          } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
              /* Inner PTE, continue walking */
-            if (pte & (PTE_D | PTE_A | PTE_U)) {
+            if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
You shouldn't need this cast

The reason that I added cast here is to avoid the possible warning for 
strict type check that pte is target_ulong( unsgined int in RV32) and  
PTE_N is always unsigned long long.

I'm not quite sure if such strict type check exists. I tested the 
operation between unsigned int and unsigned long long on gcc v 7.5.0 and 
v10.2.0 with -Wall and -Wextra. It didn't trigger any warning without  
explicit cast.

I'll delete this cast if you assist.

Regards,

Weiwei Li

                  return TRANSLATE_FAIL;
              }
              base = ppn << PGSHIFT;
@@ -716,8 +718,18 @@ restart:
              /* for superpage mappings, make a fake leaf PTE for the TLB's
                 benefit. */
              target_ulong vpn = addr >> PGSHIFT;
-            *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
-                        (addr & ~TARGET_PAGE_MASK);
+
+            if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) {
Same here

Otherwise:

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

+                napot_bits = ctzl(ppn) + 1;
+                if ((i != (levels - 1)) || (napot_bits != 4)) {
+                    return TRANSLATE_FAIL;
+                }
+            }
+
+            napot_mask = (1 << napot_bits) - 1;
+            *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
+                          (vpn & (((target_ulong)1 << ptshift) - 1))
+                         ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);

              /* set permissions on the TLB entry */
              if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
--
2.17.1