store instructions

Weiwei Li Tue, 10 May 2022 19:01:28 -0700


在 2022/3/17 下午3:47, ~eopxd 写道:

From: Yueh-Ting (eop) Chen <eop.c...@sifive.com>

Signed-off-by: eop Chen <eop.c...@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
---
  target/riscv/insn_trans/trans_rvv.c.inc |  9 +++++++
  target/riscv/vector_helper.c            | 35 +++++++++++++++++--------
  2 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 63ddd54669..9a2d54313a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -712,6 +712,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, 
uint8_t eew)
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  }

@@ -750,6 +751,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
  }

@@ -778,6 +780,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, NF, 1);
      /* Mask destination register are always tail-agnostic */
      data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  }

@@ -797,6 +800,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, NF, 1);
      /* Mask destination register are always tail-agnostic */
      data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
  }

@@ -869,6 +873,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
  }

@@ -899,6 +904,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      fn = fns[eew];
      if (fn == NULL) {
          return false;
@@ -1000,6 +1006,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, 
uint8_t eew)
      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
  }

@@ -1053,6 +1060,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
  }

@@ -1119,6 +1127,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)

      data = FIELD_DP32(data, VDATA, LMUL, emul);
      data = FIELD_DP32(data, VDATA, NF, a->nf);
      data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
      return ldff_trans(a->rd, a->rs1, data, fn, s);
  }

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c

index 934b283db2..89eea33eb3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -282,14 +282,18 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
      uint32_t esz = 1 << log2_esz;
      uint32_t total_elems = vext_get_total_elems(env, desc, esz);
      uint32_t vta = vext_vta(desc);
+    uint32_t vma = vext_vma(desc);

for (i = env->vstart; i < env->vl; i++, env->vstart++) {

-        if (!vm && !vext_elem_mask(v0, i)) {
-            continue;
-        }
-
          k = 0;
          while (k < nf) {
+            if (!vm && !vext_elem_mask(v0, i)) {
+                /* set masked-off elements to 1s */
+                vext_set_elems_1s(vd, vma,(i + k * max_elems) * esz,


seems lack a space here. the same to following cases.

Regards,

Weiwei Li

Re: [PATCH qemu v2 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

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