On Mon, 8 Apr 2024 13:58:00 +0200
Marcin Juszkiewicz wrote:
> For quite a while I am experimenting with PCI Express setup on SBSA-Ref
> system. And finally decided to write.
>
> We want to play with NUMA setup and "pxb-pcie" can be assigned to NUMA
> node other than cpu0 one. But adding it mak
On Fri, 5 Apr 2024 14:09:23 -0400
Gregory Price wrote:
> On Fri, Apr 05, 2024 at 06:44:52PM +0100, Jonathan Cameron wrote:
> > On Fri, 5 Apr 2024 12:07:45 -0400
> > Gregory Price wrote:
> >
> > > 3. (C) Upon Device receiving Release Dynamic Capacity Request
&
On Fri, 5 Apr 2024 15:43:47 -0700
"Ho-Ren (Jack) Chuang" wrote:
> On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 5 Apr 2024 00:07:06 +
> > "Ho-Ren (Jack) Chuang" wrote:
> >
> > > The current implemen
On Tue, 9 Apr 2024 12:02:31 -0700
"Ho-Ren (Jack) Chuang" wrote:
> Hi Jonathan,
>
> On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 5 Apr 2024 15:43:47 -0700
> > "Ho-Ren (Jack) Chuang" wrote:
> >
> >
On Tue, 9 Apr 2024 14:26:51 -0700
fan wrote:
> On Fri, Apr 05, 2024 at 01:18:56PM +0100, Jonathan Cameron wrote:
> > On Mon, 25 Mar 2024 12:02:27 -0700
> > nifan@gmail.com wrote:
> >
> > > From: Fan Ni
> > >
> > > To simulate FM fun
ef Performs buffer zero comparison on a DSA batch task asynchronously.
The hardware may be doing it asynchronously but unless that
buffer_zero_dsa_wait() call doesn't do what it's name suggests, this function
is wrapping the async hardware related stuff to make it synchronous.
by "cxl-inject-uncorrectable-errors" or
> >> "cxl-inject-correctable-error" is "protocol & link errors" of cxl.cachemem
> >>
>
> Many thanks
> Yuuqan
>
Yes. Note the two CXL errors are actually communicated via AER uncorrectable /
correctable internal
error combined with data that is available on the EP in the CXL specific
registers.
Jonathan
On Fri, 8 Mar 2024 13:47:47 +
Peter Maydell wrote:
> On Wed, 14 Feb 2024 at 11:16, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > Previously not all references mentioned any spec version at all.
> > Given r3.1 is the current specific
icate the value.
Fixes: Coverity ID 1534095 buffer overrun
Fixes: 8700ee15de ("hw/cxl: Standardize all references on CXL r3.1 and minor
updates")
Reported-by: Peter Maydell
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_pci.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-
On Fri, 8 Mar 2024 14:38:55 +
Peter Maydell wrote:
> On Fri, 8 Mar 2024 at 14:34, Jonathan Cameron
> wrote:
> >
> > On Fri, 8 Mar 2024 13:47:47 +
> > Peter Maydell wrote:
> > > Is there a way we could write this that would catch this error?
> &
CPI Spec 6.3, Section 5.2.16.6
>
> Suggested-by: Jonathan Cameron
Reviewed-by: Jonathan Cameron
> Signed-off-by: Ankit Agrawal
> ---
> hw/i386/acpi-build.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> ind
On Fri, 8 Mar 2024 20:35:53 -0800
fan wrote:
> On Thu, Mar 07, 2024 at 12:45:55PM +0000, Jonathan Cameron wrote:
> > ...
> >
> > > > > +list = records;
> > > > > +extents = g_new0(CXLDCExtentRaw, num_extents);
> > > >
On Wed, 13 Mar 2024 21:24:06 +0300
Michael Tokarev wrote:
> 07.03.2024 19:03, Jonathan Cameron via wrote:
> > With a numa set up such as
> >
> > -numa nodeid=0,cpus=0 \
> > -numa nodeid=1,memdev=mem \
> > -numa nodeid=2,cpus=1
> >
> > and appr
On Fri, 15 Mar 2024 09:52:28 +0800
Yuquan Wang wrote:
> Hello, Jonathan
>
> When during the test of qmps of CXL events like
> "cxl-inject-general-media-event",
> I am confuesd about the argument "flags". According to "qapi/cxl.json" in
> qemu,
og '%d': Clearing %u\n", log,
> - le16_to_cpu(payload->handles[i]));
> + le16_to_cpu(payload->handles[i-1]));
Trivial but needs spaces around the -. e.g. [i - 1]
Maybe Dan can fix up whilst applying.
Otherwise
Reviewed-by: Jonathan Cameron
>
> if (i == max_handles) {
> payload->nr_recs = i;
y device (8.2.8.5)")
> Signed-off-by: Li Zhijian
Hi,
We need to have a close look at what this is actually doing before
considering applying it. I don't have time to get that this week, but
hopefully will find some time later this month.
I don't want a partial fix for one par
on 0
> (DPA offset 128MiB) looks like below:
>
> { "execute": "cxl-release-dynamic-capacity",
> "arguments": {
> "path": "/machine/peripheral/cxl-dcd0",
> "hid": 0,
> "flags": 1,
>
t; extent is added, all the bits of the blocks in the extent will be set,
> > > which will be cleared when the extent is released.
> > >
> > > Reviewed-by: Jonathan Cameron
> > > Signed-off-by: Fan Ni
> > > ---
> > > hw/cxl/cxl-mailbox-utils.c
tor telnet:127.0.0.1:1235,server,nowait -bios QEMU_EFI.fd \
-object memory-backend-ram,size=4G,id=mem0 \
-numa node,nodeid=0,cpus=0-3,memdev=mem0
Symptoms: Nothing on console from edk2 which is built in debug mode so is
normally very noisy.
No sign of anything much happening at all
> > >
> > > ret = cxl_detect_malformed_extent_list(ct3d, in);
> > > if (ret != CXL_MBOX_SUCCESS) {
> > > +cxl_extent_group_list_delete_front(&ct3d->dc.extents_pending);
> >
> > If it's a bad message from the host, I don't think the device is supposed to
> > do anything with
On Tue, 16 Apr 2024 09:37:09 -0700
fan wrote:
> On Tue, Apr 16, 2024 at 04:00:56PM +0100, Jonathan Cameron wrote:
> > On Mon, 15 Apr 2024 10:37:00 -0700
> > fan wrote:
> >
> > > On Fri, Apr 12, 2024 at 06:54:42PM -0400, Gregory Price wrote:
> > > >
On Wed, 17 Apr 2024 13:07:35 -0700
Richard Henderson wrote:
> On 4/16/24 08:11, Jonathan Cameron wrote:
> > On Fri, 1 Mar 2024 10:41:09 -1000
> > Richard Henderson wrote:
> >
> >> If translation is disabled, the default memory type is Device, which
> >>
cdat() return boolean
> >hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean
>
> Series:
> Reviewed-by: Philippe Mathieu-Daudé
>
Acked-by: Jonathan Cameron
On Thu, 18 Apr 2024 09:15:55 +0100
Jonathan Cameron via wrote:
> On Wed, 17 Apr 2024 13:07:35 -0700
> Richard Henderson wrote:
>
> > On 4/16/24 08:11, Jonathan Cameron wrote:
> > > On Fri, 1 Mar 2024 10:41:09 -1000
> > > Richard Henderson wrote:
> > &
type is created for storing all memory types that are
> not initialized by device drivers and as a fallback.
>
> Signed-off-by: Ho-Ren (Jack) Chuang
> Signed-off-by: Hao Xiang
> Reviewed-by: "Huang, Ying"
Reviewed-by: Jonathan Cameron
a
host
or should always set the alignment without needing to pick the CAVIUM 27456
errata
which I suspect will get dropped soonish anyway if anyone ever cleans up
old errata.
Jonathan
cdat() return boolean
> >hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean
>
> Since Jonathan Ack'ed the series, I'm queuing it via my hw-misc tree.
>
Thanks,
J
On Thu, 18 Apr 2024 16:10:57 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend for DCD. All the dynamic capacity
> regions will share a single, large enough host backend. Set up address
> space for DC regions to support read/write operations to dynamic cap
On Fri, 19 Apr 2024 13:27:59 -0400
Gregory Price wrote:
> On Thu, Apr 18, 2024 at 04:10:57PM -0700, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > Add (file/memory backed) host backend for DCD. All the dynamic capacity
> > regions will share a single, large enough host backend. Set up addr
lready some Michael has seen it may speed things up.
Jonathan
p.s. Today I'm just building a tree, but will circle back around
later in the week with a final review of the last few changes.
> To simulate FM functionalities for initiating Dynamic Capacity Add
> (Opcode 5604h) and Dy
should be
straight forward anyway. My ideal is that the NUMA GP series lands early
in 9.1 cycle and this can go in parallel. I'd really like to
get this in early if possible so we can start clearing some of the other
stuff that ended up built on top of it!
Jonathan
>
> ~Gregory
On Mon, 22 Apr 2024 13:04:48 +0100
Jonathan Cameron wrote:
> On Sat, 20 Apr 2024 16:35:46 -0400
> Gregory Price wrote:
>
> > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> > > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> > &g
On Mon, 22 Apr 2024 15:23:16 +0100
Jonathan Cameron wrote:
> On Mon, 22 Apr 2024 13:04:48 +0100
> Jonathan Cameron wrote:
>
> > On Sat, 20 Apr 2024 16:35:46 -0400
> > Gregory Price wrote:
> >
> > > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
e an appropriate (maybe MCTP) interface from QEMU just
to poke the emulated device.
Jonathan
>
> Ira
>
> >
> > > Note: we skips any FM issued extent release request if the exact extent
> > > does not exist in the extent list of the device. We will loose the
>
ign closely with the data that comes from the fabric management
API in the CXL spec. So I don't see a big maintenance burden problem
in having these as stable interfaces. Whilst they aren't doing quite
the same job as the FM-API (which will be emulated such that it is
visible to the guest as that aids some other types of testing) that
interface defines the limits on what we can tell the device to do.
So yes, risk for these is minimal and I'm happy to accept that.
It'll be a while before we need libvirt to use them but I do
expect to see that happen. (subject to some guessing on a future
virtualization stack!)
Jonathan
>
> Ira
>
> [snip]
On Tue, 23 Apr 2024 12:56:21 +0200
Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > These are very similar to the recently added Generic Initiators
> > but instead of representing an initiator of memory traffic they
> > represent an edge point beyond which m
On Tue, 30 Apr 2024 08:55:12 +0200
Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > On Tue, 23 Apr 2024 12:56:21 +0200
> > Markus Armbruster wrote:
> >
> >> Jonathan Cameron writes:
> >>
> >> > These are very similar to th
On Wed, 24 Apr 2024 01:36:56 +
"Xingtao Yao (Fujitsu)" wrote:
> ping.
>
> > -Original Message-
> > From: Yao Xingtao
> > Sent: Sunday, April 7, 2024 11:07 AM
> > To: jonathan.came...@huawei.com; fan...@samsung.com
> > Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛
> > Subject: [PATCH
> Include a reference to the spec here?
>
> Is the numeric encoding of flags appropriate?
Could definitely break them out as a bunch of flags / symbolic for
the policy.
>
> In general, we prefer symbolic encodings. Numeric encodings can make
> sense when
>
> • the encodi
erently. For example, if the
> forced-removal flag is set, FM can directly get the extent back from a
> host for other uses without waiting for the host to send command to the
> device. For the above step 2, their may be not event record to the event
> log (no supported in this pa
On Tue, 7 May 2024 00:22:00 +
"Xingtao Yao (Fujitsu)" wrote:
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: Tuesday, April 30, 2024 10:43 PM
> > To: Yao, Xingtao/姚 幸涛
> > Cc: fan...@samsung.com; qemu-devel@nongnu.org
> > Su
On Wed, 8 May 2024 16:00:51 +0800
Yuquan Wang wrote:
> Hello, Jonathan
>
> Recently I run some cxl tests on qemu virt(branch:cxl-2024-04-22-draft) but
> met some
> problems.
>
> Problems:
> 1) the virt machine could not set the right numa topology from user inpu
apei_mce_report_mem_error(). Also triggers
the ghes_do_memory_failure_path() and ultimately memory_failure().
Conveniently there was a patch fixing the sync path last year
that includes info on what happens in async case.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a70297d2213253853e95f5b49651f924990c6d3b
"In addition, for aysnchronous errors, kernel will notify the
process who owns the poisoned page by sending SIGBUS with BUS_MCERRR_A0
in early kill mode."
So I think the kernel should probably do the same for CXL poison
error records when it gets them.
Jonathan
On Thu, 9 May 2024 16:35:34 +0800
Yuquan Wang wrote:
> On Wed, May 08, 2024 at 01:02:52PM +0100, Jonathan Cameron wrote:
> >
> > > [0.00] ACPI: SRAT: Node 0 PXM 0 [mem 0x4000-0xbfff]
> > > [0.00] ACPI: SRAT: Node 1 PXM 1 [mem 0xc000-0x13f
On Mon, 9 Jan 2023 11:15:28 -0800
Ira Weiny wrote:
> On Tue, Jan 03, 2023 at 06:07:19PM +0000, Jonathan Cameron wrote:
> > On Wed, 21 Dec 2022 20:24:38 -0800
> > Ira Weiny wrote:
> >
> > > To facilitate testing provide a QMP command to inject a general media
d some reworks I mentioned in this thread.
Note there is a dirty hack on top of that tree to deal with a build issue on my
arch-linux
test box that I foolishly upgraded this morning. Might break things on other
distros
(version issue with curl).
Jonathan
>
> Jonathan
>
> >
&
Price (2):
hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition
Ira Weiny (3):
qemu/bswap: Add const_le64()
qemu/uuid: Add UUID static initializer
hw/cxl/mailbox: Use new UUID network order define for cel_uuid
Jonathan Cameron (3):
h
msix_init_exclusive_bar() can fail, so if it does cleanup the address space.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index dae4fd89ca..252822bd82 100644
--- a
Fix capitalization difference between struct name and typedef.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_downstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
index 3d4e6b59cd..54f507318f
From: Gregory Price
Current code sets to STORAGE_EXPRESS and then overrides it.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem
From: Gregory Price
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 14
Noticed as this prevents iASL disasembling the DSDT table.
Signed-off-by: Jonathan Cameron
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 127c4e2d50..a584b62ae2 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi
From: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Reviewed-by: Peter Maydell
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
include/qemu/bswap.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/qemu/bswap.h b
ff-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-device-utils.c | 2 +-
hw/cxl/cxl-mailbox-utils.c | 13 ++---
include/hw/cxl/cxl_device.h | 2 +-
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
From: Ira Weiny
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
include/qemu/u
On Wed, 11 Jan 2023 17:40:46 +0100
Philippe Mathieu-Daudé wrote:
> On 11/1/23 15:24, Jonathan Cameron via wrote:
> > From: Ira Weiny
> >
> > Gcc requires constant versions of cpu_to_le* calls.
> >
> > Add a 64 bit version.
> >
> > Reviewed-by
From: Ira Weiny
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
include/qemu/u
/qemu/-/commits/cxl-2023-01-11
Gregory Price (2):
hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition
Ira Weiny (3):
qemu/bswap: Add const_le64()
qemu/uuid: Add UUID static initializer
hw/cxl/mailbox: Use new UUID network order define for
Noticed as this prevents iASL disasembling the DSDT table.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 127c4e2d50..a584b62ae2 100644
--- a/hw/i386/acpi
From: Gregory Price
Current code sets to STORAGE_EXPRESS and then overrides it.
Reviewed-by: Davidlohr Bueso
Reviewed-by: Ira Weiny
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw
From: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
v2: Update comment (Philippe)
include/qemu/bswap.h | 12 +++-
1
From: Gregory Price
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Signed-off-by: Jonathan Cameron
---
v2:
Change to 256 * MiB and include qemu
msix_init_exclusive_bar() can fail, so if it does cleanup the address space.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index dae4fd89ca
Fix capitalization difference between struct name and typedef.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_downstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
ed-by: Philippe Mathieu-Daudé
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
v2:
Make it const (Philippe)
hw/cxl/cxl-device-utils.c | 2 +-
hw/cxl/cxl-mailbox-utils.c | 13 ++---
include/hw/cxl/cxl_device.h | 2 +-
3 files changed, 8 insertions(+), 9 deletions(-)
diff
On Wed, 21 Dec 2022 20:24:38 -0800
Ira Weiny wrote:
> To facilitate testing provide a QMP command to inject a general media
> event. The event can be added to the log specified.
>
> Signed-off-by: Ira Weiny
Hi Ira,
One thing inline that kind of came out of Philippe's review of
the earlier cle
On Thu, 12 Jan 2023 10:39:17 -0500
Gregory Price wrote:
> On Wed, Jan 11, 2023 at 02:24:32PM +0000, Jonathan Cameron via wrote:
> > Gregory's patches were posted as part of his work on adding volatile
> > support.
> > https://lore.kernel.org/linux-cxl/2022100
; Signed-off-by: Markus Armbruster
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Bin Meng
> Reviewed-by: Taylor Simpson
> Reviewed-by: Alistair Francis
For the CXL one.
Acked-by: Jonathan Cameron
> ---
> bsd-user/qemu.h | 1 -
> crypto/block-luks-
On Thu, 12 Jan 2023 17:46:27 -0500
Gregory Price wrote:
> On Thu, Jan 12, 2023 at 05:21:30PM +0000, Jonathan Cameron wrote:
> > On Thu, 12 Jan 2023 10:39:17 -0500
> > Gregory Price wrote:
> >
> > > On Wed, Jan 11, 2023 at 02:24:32PM +, Jonathan Cameron
x27;s the configuration that would have
worked. However I would want to keep the option to enable these decoders
around. I can spin up a patch or do you want to do it? My suggestion is option
1 with default being no HDM decoder.
Jonathan
> ---
> hw/cxl/cxl-host.c | 7 +--
> 1 fi
On Fri, 13 Jan 2023 14:40:26 +
Jonathan Cameron wrote:
> On Fri, 13 Jan 2023 09:19:59 -0500
> Gregory Price wrote:
>
> > On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Cameron wrote:
> > >
> > > Just to check, are these different from
On Fri, 13 Jan 2023 09:19:59 -0500
Gregory Price wrote:
> On Fri, Jan 13, 2023 at 09:12:13AM +0000, Jonathan Cameron wrote:
> >
> > Just to check, are these different from the on stack problem you reported
> > previously? Doesn't look like the fix for tha
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "phys
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 4
include/hw/pci/pcie_r
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mem/cxl_type3.c
quot;: "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": &quo
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h
lass bit in the PCIe
Device Control Register is set.
Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 10 +-
1 file changed, 9 insertions(+),
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge
*/
> > +if (!QTAILQ_EMPTY(&ct3d->error_list)) {
> > +CXLError *cxl_err = QTAILQ_FIRST(&ct3d->error_list);
>
> Is it ok that "CXLError *cxl_err" definition clobbers previous one above?
It isn't a bug as the external one is only used much later in a QTAILQ_FOREACH()
to build the resulting error status register, but it's certainly inelegant
and there is no need for the internal definition so I'll drop it.
I also moved the assignment to the else leg which is the only place that
specific assignment is used.
Thanks for quick review! I'll hold off sending a v2 out for a day or two
to let any other early comments come in.
Jonathan
On Fri, 13 Jan 2023 17:10:51 +
Fan Ni wrote:
> On Fri, Jan 13, 2023 at 09:47:25AM +0000, Jonathan Cameron wrote:
>
> > On Fri, 13 Jan 2023 00:27:55 +
> > Fan Ni wrote:
> >
> > > For passthrough decoder (a decoder hosted by a cxl component with onl
On Wed, 18 Jan 2023 14:22:08 -0500
Gregory Price wrote:
> 1) No stack traces present
> 2) Device usage appears to work, but cxl-cli fails to create a region, i
> haven't checked why yet (also tried ndctl-75, same results)
> 3) There seems to be some other regression with the cxl_pmem_init
> routi
On Thu, 19 Jan 2023 06:48:11 -0500
"Michael S. Tsirkin" wrote:
> On Thu, Jan 19, 2023 at 10:19:46AM +0000, Jonathan Cameron wrote:
> > On Wed, 18 Jan 2023 14:22:08 -0500
> > Gregory Price wrote:
> >
> > > 1) No stack traces present
> > > 2) D
0000 x6 :
x5 : 88923a84 x4 : 000c x3 : 88923a10
x2 : x1 : x0 : 0070
Call trace:
cxl_pmem_ctl+0x74/0x244 [cxl_pmem]
nvdimm_init_nsarea+0xb8/0xdc
nvdimm_probe+0xc0/0x1d0
nvdimm_bus_probe+0x
On Thu, 19 Jan 2023 12:42:44 +
Jonathan Cameron via wrote:
> On Wed, 18 Jan 2023 14:31:53 -0500
> Gregory Price wrote:
>
> > I apparently forgot an intro lol
> >
> > I tested the DOE linux branch with the 2023-1-11 QEMU branch with both
> > volatile, n
On Thu, 19 Jan 2023 15:04:49 +
Jonathan Cameron wrote:
> On Thu, 19 Jan 2023 12:42:44 +
> Jonathan Cameron via wrote:
>
> > On Wed, 18 Jan 2023 14:31:53 -0500
> > Gregory Price wrote:
> >
> > > I apparently forgot an intro lol
> > >
On Thu, 19 Jan 2023 12:15:45 -0500
Gregory Price wrote:
> Found a bug, not sure how we missed this, probably happed with rebasing
> and some fixups. We're presently reporting the volatile region as
> non-volatile, 1 line patch.
>
> Jonathan do you want a separate patch
On Thu, 19 Jan 2023 23:53:53 -0500
Gregory Price wrote:
> On Thu, Jan 19, 2023 at 03:04:49PM +0000, Jonathan Cameron wrote:
> > Gregory, would you mind checking if
> > cxl_nvb is NULL here...
> > https://elixir.bootlin.com/linux/v6.2-rc4/source/drivers/cxl/pmem.c#L67
>
On Thu, 19 Jan 2023 17:13:40 -0500
Gregory Price wrote:
> On Thu, Jan 19, 2023 at 05:31:12PM +0000, Jonathan Cameron wrote:
> > On Thu, 19 Jan 2023 12:15:45 -0500
> > Gregory Price wrote:
> >
> > > Found a bug, not sure how we missed this, probably happed with
execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical",
"header": [ 3, 4]
} }
Based on top of:
https://lore.kernel.org/
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 4
include/hw/pci/pcie_r
lass bit in the PCIe
Device Control Register is set.
Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 10 +-
1 file changed, 9 insertions(+),
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mem/cxl_type3.c
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "phys
On Wed, 22 Mar 2023 16:21:26 +
Fan Ni wrote:
> On Wed, Mar 22, 2023 at 10:33:00AM +0000, Jonathan Cameron wrote:
> > The hardware clearing the commit bit is not spec compliant.
> > Clearing of committed bit when commit is cleared is not specifically
> > stated in the
On Fri, 24 Mar 2023 04:32:52 +0530
Maverickk 78 wrote:
> Hello Jonathan
>
> Raghu here, I'm going over your cxl patches for past few days, it's very
> impressive.
>
> I want to get involved and contribute in your endeavor, may be bits &
> pieces to start.
&
601 - 700 of 2719 matches
Mail list logo
