deprecations not (yet) tackled.
The Xen tools maintainers will need to be more vigilant of the deprecations. I
don't follow Xen development close enough to know if this topic has already been
discussed.
Regards,
Jim
atx) and it worked well for me running the gcc testsuite for a
riscv32-linux target. I haven't tried testing the latest version of the
patch yet. I can do that if this is helpful.
Jim
32-bit RISC-V uses _llseek instead of lseek as syscall number 62.
Update syscall list from open-embedded build, primarily because
32-bit RISC-V requires statx support.
Tested with cross gcc testsuite runs for rv32 and rv64, with the
pending statx patch also applied.
Signed-off-by: Jim Wilson
linux toolchain.
Signed-off-by: Jim Wilson
---
linux-user/strace.c| 86 ++
linux-user/strace.list | 3 ++
2 files changed, 89 insertions(+)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 6f72a74..c80e93b 100644
--- a/linux-user/str
to
attribute unused, but this is the exact same C syntax used in the rest
of the file. I think this is a bug in the checkpatch script as this
looks like it should be allowed. Or maybe there is an exception for
this one file?
Jim
I submitted it the usual way, so it is on the mailing list now. If
you want to include it with your patch series that is fine.
https://lists.nongnu.org/archive/html/qemu-devel/2019-06/msg04087.html
Jim
dif
> result = riscv_csrrw(env, ...);
> #if !defined(CONFIG_USER_ONLY)
> env->debugger = false;
> #endif
> }
Yes, that would work. Do you want me to resubmit a fixed part 5 patch?
Jim
This is the 4th version of the patch set. Updated as per the review
from Alistair, it has the riscv_csrrw_debug function added, and
Reviewed-By lines added. Otherwise it is the same as the 3rd version.
Jim
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43
gdb-xml/riscv-32bit-csr.xml | 250
gdb-xml/riscv-32bit-fpu.xml | 46
4 files changed, 340
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/target
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
Signed-off-by: Jim Wilson
---
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43
gdb-xml/riscv-64bit-csr.xml | 250
gdb-xml/riscv-64bit-fpu.xml | 52 +
4 files changed, 346
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/csr.c | 34 ++
2 files
file and the registers in it. Likewise for the 64-bit support.
The main advantage of doing things this way is that only people that
care about the priv register will see it, and this will interoperate
with other RISC-V debuggers and targets (if any) that already have
virtual priv register support.
Jim
r set. Shrug. Anyways, defining priv as a virtual
register is the right way to do this, as it isn't a cpu register, and
gdb already has support for virtual registers like priv.
Jim
xpected. So this
looks good to me.
I'm leaving on a trip tomorrow, and only taking one laptop with me, so
I won't have access to my Ubuntu 19 machine anymore.
Jim
n it probably should
be discussed with the gdb developers too, so that the gdb and qemu
copies of the files remain consistent.
Fixing the rvf/rvd 32/64-bit support is good. That is a bug in my
original implementation.
Jim
-bit.
To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
riscv_gdb_set_fpu() were necessary.
Reviewed-by: Jim Wilson
Jim
n just remove all of this work when the official rvv spec if
available? But presumably it is better if we can have both this
implementation and the official one, which means everything needs to be
conditional or tied to an Xsomething extension name instead of the V
extension name.
Jim
n 0;
+}
This is wrong for the current spec, because the vector status bits
aren't in the FCSR anymore. So this also needs to be rvv 0.7.1 specific.
Jim
of the vector spec. x0 now means
don't change VL. So this needs to be version specific.
Jim
On Wed, Feb 26, 2020 at 2:36 PM Alistair Francis wrote:
> On Wed, Feb 26, 2020 at 12:09 PM Jim Wilson wrote:
> > If this rvv 0.7.1 implementation is considered a temporary solution,
> > maybe we can just remove all of this work when the official rvv spec if
> > available?
This is simply an
implementation choice so you can use static arrays instead of malloc. I
think this error should be reworded to something like "Vector extension
implementation only supports VLEN <= %d."
The other errors here are for architecture requirements and are OK.
Jim
ays depending on whether we have only
F, only V, or both F and V. And then we can support reads and writes of
only the valid fields.
Jim
e that there is a ATTRIBUTE_UNUSED in the disas dir
but it is apparently not used outside there, and only defined in
include/disas/bfd.h. I see a few scattered uses of
attribute((unused)) but that seems unwise for portability reasons.
Maybe qemu doesn't care about unused arguments/parameters?
Jim
On 5/16/2019 9:04 PM, Thomas Huth wrote:
On 10/05/2019 12.46, Gerd Hoffmann wrote:
This patch series changes the way virtual machines for test builds are
managed. They are created locally on the developer machine now. The
installer is booted on the serial console and the scripts walks through
lem of figuring out exactly which CSRs a particular
target implements, which is a bigger problem than I have time to fix
at the moment, and should be handled as a separate problem.
Since my patch set is now a month old, I'll rebase onto current master
and post a version 3 patch set.
Jim
before, just arranged
differently, so this shouldn't complicate the review too much.
Jim
s a
result of this, part 4 also ends up smaller, and part 5 is rewritten a
bit to use the new interface to the csr support. Otherwise it is
effectively the same code as before.
Jim
Signed-off-by: Jim Wilson
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43
gdb-xml/riscv-32bit-csr.xml | 250
gdb-xml/riscv-32bit-fpu.xml | 46
4 files changed, 340 insertions(+)
create mode 100644 gdb
Signed-off-by: Jim Wilson
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43
gdb-xml/riscv-64bit-csr.xml | 250
gdb-xml/riscv-64bit-fpu.xml | 52 +
4 files changed, 346 insertions(+)
create mode 100644 gdb
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson
---
target/riscv/cpu_bits.h | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv
Adds a debugger field to CPURISCVState. Disable mode checks in riscv_csrrw
when true.
Signed-off-by: Jim Wilson
---
target/riscv/cpu.h | 3 +++
target/riscv/csr.c | 16
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
Signed-off-by: Jim Wilson
---
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 8 ++--
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifiv
The cells of 'initrd-start/end' should follow the '#address-cell'.
QEMU API could support 1 and 2 cells.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index ad
Support to load DTB after 3GB on RV64 system, so that larger initrd
doesn't be overlapped to DTB. Update initrd DT to support different
"#address-cells".
Verify the patch via running 4GB initramfs on the virt machine.
Jim Shu (2):
hw/riscv: Support to load DTB after 3GB memory o
On Mon, Oct 21, 2024 at 9:42 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/21/24 1:09 AM, Jim Shu wrote:
> > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
> > system doesn't have 32-bit addressable issue, we just load DTB to the end
in.com/linux/v6.11.4/source/drivers/of/fdt.c#L785
[2] https://elixir.bootlin.com/linux/v6.11.4/source/drivers/of/fdt.c#L857
Thanks,
Jim Shu
On Tue, Oct 22, 2024 at 3:30 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/21/24 1:09 AM, Jim Shu wrote:
> > The cells of 'initrd-
Reviewed-by: Jim Shu
On Tue, Sep 24, 2024 at 9:24 PM Andrew Jones wrote:
>
> On Tue, Sep 24, 2024 at 04:30:01PM GMT, zhouq...@iscas.ac.cn wrote:
> > From: Quan Zhou
> >
> > Add support for a few Zc* extensions, Zimop, Zcmop and Zawrs.
> >
> > Signed-off-by:
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 66 ++
hw/riscv/microchip_pfsoc.c | 11 ++---
hw/riscv/opentitan.c | 4 +-
hw/riscv
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 8 ++--
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifiv
cking and struct RISCVBootInfo
- Remove the commit to change #address-cell of 'initrd-[start|end]'
Jim Shu (3):
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
hw/riscv: Add a new struct RISCVBootInfo
hw/riscv: Add the checking if DTB overlaps to kernel or initrd
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c | 24 +++-
include/hw/riscv/boot.h | 3 +++
2 files changed, 26 insertions(+), 1 deletion(-)
diff
On Fri, Nov 8, 2024 at 5:33 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 11/7/24 3:31 AM, Jim Shu wrote:
> > Add a new struct RISCVBootInfo to sync boot information between multiple
> > boot functions.
> >
> > Signed-off-by: Jim Shu
> > ---
>
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 65 +-
hw/riscv/microchip_pfsoc.c | 12 +++---
hw/riscv/opentitan.c | 5 ++-
hw/riscv
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 8 ++--
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifiv
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c | 25 -
include/hw/riscv/boot.h | 3 +++
2 files changed, 27 insertions(+), 1 deletion(-)
diff
tInfo from machine state to local variables.
Changes for v2:
- Add DTB overlapping checking and struct RISCVBootInfo
- Remove the commit to change #address-cell of 'initrd-[start|end]'
Jim Shu (3):
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
hw/riscv: A
On Tue, Nov 12, 2024 at 5:53 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 11/8/24 4:04 AM, Jim Shu wrote:
> > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
> > system doesn't have 32-bit addressable issue, we just load DTB to the end
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 65 ++
hw/riscv/microchip_pfsoc.c | 11 ---
hw/riscv/opentitan.c | 4 ++-
hw/riscv/sifive_e.c
On Tue, Nov 12, 2024 at 6:05 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 11/8/24 4:04 AM, Jim Shu wrote:
> > Add a new struct RISCVBootInfo to sync boot information between multiple
> > boot functions.
> >
> > Signed-off-by: Jim Shu
> > ---
>
and struct RISCVBootInfo
- Remove the commit to change #address-cell of 'initrd-[start|end]'
Jim Shu (3):
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
hw/riscv: Add a new struct RISCVBootInfo
hw/riscv: Add the checking if DTB overlaps to kernel or init
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 14 +-
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c | 25 -
include/hw/riscv/boot.h | 3 +++
2 files changed, 27 insertions(+), 1 deletion(-)
diff
Hi,
Gentle ping on this patch
Thanks,
Jim Shu
On Wed, Nov 20, 2024 at 11:39 PM Jim Shu wrote:
>
> Support to load DTB after 3GB on RV64 system, so that larger initrd
> doesn't be overlapped to DTB. DTB loading now will check if overlapping
> to kernel/initrd and
I'm sorry for the wrong ping.
The email to apply my patch is placed in the spam mail
On Tue, Dec 17, 2024 at 12:01 PM Jim Shu wrote:
>
> Hi,
>
> Gentle ping on this patch
>
> Thanks,
> Jim Shu
>
>
>
>
>
> On Wed, Nov 20, 2024 at 11:39 PM Jim Shu
This is the correct fix, thanks!
On Tue, Dec 17, 2024 at 11:39 AM Alistair Francis wrote:
>
> On Thu, Nov 21, 2024 at 1:41 AM Jim Shu wrote:
> >
> > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
> > system doesn't have 32-bit addressable i
Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR.
Signed-off-by: Jim Shu
---
target/riscv/csr.c | 44
target/riscv/time_helper.c | 51
VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will
revert it's defined behavior as if sstc extension is not implemented.
Signed-off-by: Jim Shu
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/t
When changing the mtime value, the period of [s|vs]timecmp timers
should also be updated like the period of mtimecmp timer.
Signed-off-by: Jim Shu
---
hw/intc/riscv_aclint.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index db374a7c2d
Preparation commit to let aclint timer to use stimecmp write function.
Aclint timer doesn't call sstc() predicate so we need to check inside
the stimecmp write function.
Signed-off-by: Jim Shu
---
target/riscv/time_helper.c | 19 +--
1 file changed, 17 insertions(+), 2 dele
,
which should update the timer and IRQ pending bits.
Jim Shu (4):
target/riscv: Add the checking into stimecmp write function.
hw/intc: riscv_aclint: Fix mtime write for sstc extension
target/riscv: Fix VSTIP bit in sstc extension.
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit
Hi,
Gentle ping on this patch.
Thanks,
Jim Shu
On Thu, Mar 20, 2025 at 3:22 AM Jim Shu wrote:
>
> This patch series contains several sstc fixes:
>
> (1) Writing to ACLINT mtime should also update the period of S/VS-mode
> timer, just like M-mode timer.
> (2) VSTIP bit
OK, I will fix it in the v2 patchset.
Jim Shu
On Fri, Apr 4, 2025 at 2:03 PM Alistair Francis wrote:
>
> On Thu, Mar 20, 2025 at 5:24 AM Jim Shu wrote:
> >
> > Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
> > also need to update S/VS-mode T
c ch19.2.1. Virtual Supervisor Timer (vstimecmp) Register
A virtual supervisor timer interrupt becomes pending, as reflected in
the VSTIP bit in the hip register, whenever (time + htimedelta),
truncated to 64 bits, contains a value greater than or equal to
vstimecmp
Signed-off-by: Jim Shu
---
hw/in
Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR.
Signed-off-by: Jim Shu
---
target/riscv/csr.c | 44
target/riscv/time_helper.c | 46
Preparation commit to let aclint timer to use stimecmp write function.
Aclint timer doesn't call sstc() predicate so we need to check inside
the stimecmp write function.
Signed-off-by: Jim Shu
Acked-by: Alistair Francis
---
target/riscv/time_helper.c | 19 +--
1 file ch
VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will
revert it's defined behavior as if sstc extension is not implemented.
Signed-off-by: Jim Shu
Acked-by: Alistair Francis
---
target/riscv/csr.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --
Sorry, I forgot to write v2 changes in cover-letter.
Changes in v2:
- Remove duplicated code in riscv_timer_stce_changed() function
- Add sstc spec description in the commit log
On Wed, Apr 9, 2025 at 10:51 AM Jim Shu wrote:
>
> This patch series contains several sstc fixes:
>
> (1
,
which should update the timer and IRQ pending bits.
Jim Shu (4):
target/riscv: Add the checking into stimecmp write function.
hw/intc: riscv_aclint: Fix mtime write for sstc extension
target/riscv: Fix VSTIP bit in sstc extension.
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit
VSTIP bit in the hip register, whenever (time + htimedelta),
truncated to 64 bits, contains a value greater than or equal to
vstimecmp
I will add the explaination in the commit log in the v2 patchset, thanks.
Jim Shu
On Fri, Apr 4, 2025 at 11:12 AM Alistair Francis wrote:
>
> On Thu, Ma
wgChecker slot is similar to PMP region. SW could program each slot to
configure the permission of address range.
Signed-off-by: Jim Shu
---
hw/misc/riscv_wgchecker.c | 330 +
hw/misc/riscv_worldguard.c | 3 +
include/hw/misc/riscv_worldguard.h
Hi Richard,
Thank you very much for adding atomic support to translator_ld(). It
has been a big help.
Hi Alistair,
I can rebase the Ziccif patch when Richard's patch has been merged.
Jim Shu
On Fri, Apr 4, 2025 at 12:41 PM Alistair Francis wrote:
>
> On Fri, Jun 7, 2024 at 8:15
nce they are only in the
path of DMA access. Currently, the bug only occurs when ARM MPC device
(hw/misc/tz-mpc.c) returns 'blocked_io_as' to emulate blocked access
handling. Upcoming RISC-V wgChecker device is also affected by this bug.
Signed-off-by: Jim Shu
---
accel/tcg/cputlb.c |
WG after WG CPU code has been implemented
- Change 'mwid' and 'mwidlist' options to experimental options
- Change 'world_id' to unsigned int type + bit field.
Jim Shu (18):
accel/tcg: Store section pointer in CPUTLBEntryFull
system/physmem: Remove the assertion of pag
We define CPU options for WG CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating WG CSRs.
Signed-off-by: Jim Shu
---
target/riscv/cpu.c | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv
* Add 'wg=on' option to enable RISC-V WorldGuard
* Add wgChecker to protect several resources:
DRAM, FLASH, UART.
Signed-off-by: Jim Shu
---
docs/system/riscv/virt.rst | 20 +
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c
riscv_worldguard_apply_cpu() could enable WG CPU extension and set WG
callback to CPUs. It is used by machine code after realizing global WG
device.
Signed-off-by: Jim Shu
---
hw/misc/riscv_worldguard.c | 87 ++
include/hw/misc/riscv_worldguard.h | 1 +
2
that point.
One tricky part here is that the perm of 'blocked_io_as' is the
condition of deny access. For example, if wgChecker only permits RO
access, the perm of 'downstream_as' will be IOMMU_RO and the perm of
'blocked_io_as' will be IOMMU_WO.
Signed
Expose WG CPU extensions (Smwg, Sswg, Smwgd) and WG CPU configs
(mwid, mwidlist).
Signed-off-by: Jim Shu
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1aba6dd853..46df970fe3 100644
--- a/target/riscv/cpu.c
+++ b
Add CSRs for 3 WG extensions: Smwg, Smwgd, and Sswg.
Signed-off-by: Jim Shu
---
target/riscv/cpu_bits.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a30317c617..7705c6995e 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv
The wgChecker is configurable for whether blocked accesses:
* should cause a bus error or just read return zero and write ignore
* should generate the interrupt or not
Signed-off-by: Jim Shu
---
hw/misc/riscv_wgchecker.c | 169 +-
1 file changed, 167
s, we should
set it by machine code.
Signed-off-by: Jim Shu
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 ++
3 files changed, 22 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 51e49e03de..ac5092
The physical section number is no longer ORed into the IOTLB entries
together with a page-aligned pointer, so it no longer needs to be
page-aligned.
Signed-off-by: Jim Shu
---
system/physmem.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/system/physmem.c b/system/physmem.c
index
The WG v0.4 specification adds 3 CSRs to configure S/U/HS/VS-mode WIDs
of CPUs in the higher privileged modes.
The Smwg extension at least requires a RISC-V HART to have M/U-mode, and
the Sswg/Smwgd extension at least requires a RISC-V HART to have
M/S/U-mode.
Signed-off-by: Jim Shu
---
target
When a RISC-V HART has WG extension, their memory transactions will
contain WID. Support MemTxAttrs in RISC-V target and add WID inside if
a HART has WG extension.
Signed-off-by: Jim Shu
---
target/riscv/cpu.c| 2 +-
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 51
Some WG CPU functions depend on global WG config (like num-of-world), so
we let the global WG config device to set callbacks of a RISC-V HART.
Signed-off-by: Jim Shu
---
target/riscv/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
Add a device for RISCV WG global config, which contains the number of
worlds, reset value, and trusted WID ... etc.
This global config is used by both CPU WG extension and wgChecker devices.
Signed-off-by: Jim Shu
---
hw/misc/Kconfig| 3 +
hw/misc/meson.build
tion so that IOMMU could return the correct section
of specified access_type.
Signed-off-by: Jim Shu
---
accel/tcg/cputlb.c | 17 ++---
include/exec/cputlb.h| 11 +++
include/exec/exec-all.h | 3 ++-
system/physm
signal.
Signed-off-by: Jim Shu
---
include/exec/memattrs.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 8db1d30464..7a6866fa41 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -54,6 +54,11
ansactions
Signed-off-by: Jim Shu
---
hw/misc/meson.build| 2 +-
hw/misc/riscv_wgchecker.c | 603 +
hw/misc/trace-events | 8 +
include/hw/misc/riscv_worldguard.h | 63 +++
4 files changed, 675 insertions(+), 1 deletion(-)
c
more than 4k sections.
I think my commit should also remove the `iotlb_to_section()` function
and rename `xlat_section` to `xlat`.
I will fix it in the next patch.
[1] https://github.com/qemu/qemu/commit/68f3f65b09a1ce8c82fac17911ffc3bb6031ebe4
Jim
On Tue, Apr 15, 2025 at 5:13 PM Ilya Leoshk
s, we should
set it by machine code.
Signed-off-by: Jim Shu
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 ++
3 files changed, 22 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 51e49e03de..ac5092
We define CPU options for WG CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating WG CSRs.
Signed-off-by: Jim Shu
---
target/riscv/cpu.c | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv
tion so that IOMMU could return the correct section
of specified access_type.
Signed-off-by: Jim Shu
---
accel/tcg/cputlb.c | 17 ++---
include/exec/cputlb.h| 11 +++
include/exec/exec-all.h | 3 ++-
system/physm
Some WG CPU functions depend on global WG config (like num-of-world), so
we let the global WG config device to set callbacks of a RISC-V HART.
Signed-off-by: Jim Shu
---
target/riscv/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
Add a device for RISCV WG global config, which contains the number of
worlds, reset value, and trusted WID ... etc.
This global config is used by both CPU WG extension and wgChecker devices.
Signed-off-by: Jim Shu
---
hw/misc/Kconfig| 3 +
hw/misc/meson.build
* Add 'wg=on' option to enable RISC-V WorldGuard
* Add wgChecker to protect several resources:
DRAM, FLASH, UART.
Signed-off-by: Jim Shu
---
docs/system/riscv/virt.rst | 20 +
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c
wgChecker slot is similar to PMP region. SW could program each slot to
configure the permission of address range.
Signed-off-by: Jim Shu
---
hw/misc/riscv_wgchecker.c | 330 +
hw/misc/riscv_worldguard.c | 3 +
include/hw/misc/riscv_worldguard.h
301 - 400 of 728 matches
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