This patchset implements Smwg/Smwgd/Sswg CPU extension and wgChecker device defined in WorldGuard spec v0.4.
The WG v0.4 spec could be found here: https://lists.riscv.org/g/security/attachment/711/0/worldguard_rvia_spec-v0.4.pdf To enable WG in QEMU, pass "wg=on" as machine parameter to virt machine. It enables both WG CPU CSRs to apply WID of CPU and wgCheckers on the DRAM, FLASH, and UART to protect these resources. This patchset contains 5 parts: 1. Commit 1 ~ 2: Bugfix of IOMMUMemoryRegion 2. Commit 3 ~ 4: Extend IOMMUMemoryRegion and MemTxAttr for WG support 3. Commit 5 ~ 13: Add WG global device and CPU extensions 4. Commit 14 ~ 17: Add WG checker device 5. Commit 18: Add WG support to the virt machine QEMU code can be found at [1] [1] https://github.com/cwshu/qemu/tree/riscv-wg-v2 Changed since v1: - Remove the assertion of 4k sections limitation. Remove iotlb_to_section() and rename 'xlat_section' to 'xlat'. - Fix RST issue and typo in virt machine doc Changed since RFCv1: - Rebase to latest QEMU (v10.0.0-rc3) - Add the description of HW config and CPU option of WG in the virt machine documentation - Expose CPU options of WG after WG CPU code has been implemented - Change 'mwid' and 'mwidlist' options to experimental options - Change 'world_id' to unsigned int type + bit field. Jim Shu (18): accel/tcg: Store section pointer in CPUTLBEntryFull system/physmem: Remove the assertion of page-aligned section number accel/tcg: memory access from CPU will pass access_type to IOMMU exec: Add RISC-V WorldGuard WID to MemTxAttrs hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config target/riscv: Add CPU options of WorldGuard CPU extension target/riscv: Add hard-coded CPU state of WG extension target/riscv: Add defines for WorldGuard CSRs target/riscv: Allow global WG config to set WG CPU callbacks target/riscv: Implement WorldGuard CSRs target/riscv: Add WID to MemTxAttrs of CPU memory transactions target/riscv: Expose CPU options of WorldGuard hw/misc: riscv_worldguard: Add API to enable WG extension of CPU hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker hw/misc: riscv_wgchecker: Implement wgchecker slot registers hw/misc: riscv_wgchecker: Implement correct block-access behavior hw/misc: riscv_wgchecker: Check the slot settings in translate hw/riscv: virt: Add WorldGuard support accel/tcg/cputlb.c | 49 +- docs/system/riscv/virt.rst | 20 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/riscv_wgchecker.c | 1160 ++++++++++++++++++++++++++ hw/misc/riscv_worldguard.c | 272 ++++++ hw/misc/trace-events | 9 + hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 163 +++- include/exec/cputlb.h | 13 +- include/exec/exec-all.h | 18 +- include/exec/memattrs.h | 8 +- include/hw/core/cpu.h | 12 +- include/hw/misc/riscv_worldguard.h | 123 +++ include/hw/riscv/virt.h | 15 +- system/physmem.c | 39 +- target/alpha/helper.c | 2 +- target/avr/helper.c | 2 +- target/hppa/mem_helper.c | 1 - target/i386/tcg/system/excp_helper.c | 3 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/helper.c | 10 +- target/microblaze/helper.c | 8 +- target/mips/tcg/system/tlb_helper.c | 4 +- target/openrisc/mmu.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/riscv/cpu.c | 17 +- target/riscv/cpu.h | 12 + target/riscv/cpu_bits.h | 5 + target/riscv/cpu_cfg.h | 5 + target/riscv/cpu_helper.c | 69 +- target/riscv/csr.c | 107 +++ target/riscv/tcg/tcg-cpu.c | 11 + target/rx/cpu.c | 3 +- target/s390x/tcg/excp_helper.c | 2 +- target/sh4/helper.c | 2 +- target/sparc/mmu_helper.c | 6 +- target/tricore/helper.c | 2 +- target/xtensa/helper.c | 3 +- 39 files changed, 2074 insertions(+), 112 deletions(-) create mode 100644 hw/misc/riscv_wgchecker.c create mode 100644 hw/misc/riscv_worldguard.c create mode 100644 include/hw/misc/riscv_worldguard.h -- 2.17.1
