I'm sorry for the wrong ping. The email to apply my patch is placed in the spam mail....
On Tue, Dec 17, 2024 at 12:01 PM Jim Shu <jim....@sifive.com> wrote: > > Hi, > > Gentle ping on this patch > > Thanks, > Jim Shu > > > > > > On Wed, Nov 20, 2024 at 11:39 PM Jim Shu <jim....@sifive.com> wrote: > > > > Support to load DTB after 3GB on RV64 system, so that larger initrd > > doesn't be overlapped to DTB. DTB loading now will check if overlapping > > to kernel/initrd and report this error. > > > > Verify the patch via running 4GB initramfs on the virt machine. > > > > > > Changes for v4: > > > > - Update the comments of loading DTB in 64-bit CPU > > - Align image_[low|high]_addr's type with initrd_start (hwaddr) > > - Fix commit 2 to avoid unnecessary change .h file of board > > > > Changes for v3: > > > > - Change struct RISCVBootInfo from machine state to local variables. > > > > Changes for v2: > > > > - Add DTB overlapping checking and struct RISCVBootInfo > > - Remove the commit to change #address-cell of 'initrd-[start|end]' > > > > Jim Shu (3): > > hw/riscv: Support to load DTB after 3GB memory on 64-bit system. > > hw/riscv: Add a new struct RISCVBootInfo > > hw/riscv: Add the checking if DTB overlaps to kernel or initrd > > > > hw/riscv/boot.c | 100 +++++++++++++++++++++++++------------ > > hw/riscv/microchip_pfsoc.c | 13 +++-- > > hw/riscv/opentitan.c | 4 +- > > hw/riscv/sifive_e.c | 4 +- > > hw/riscv/sifive_u.c | 14 +++--- > > hw/riscv/spike.c | 14 +++--- > > hw/riscv/virt.c | 13 +++-- > > include/hw/riscv/boot.h | 28 ++++++++--- > > 8 files changed, 127 insertions(+), 63 deletions(-) > > > > -- > > 2.17.1 > >
