there any issue with output format?
3. Is it fine to add only for HMP, but not QMP?
Thank you very much!
Dongli Zhang
: Dongli Zhang
---
hmp-commands-info.hx | 13 +++
hw/pci/msix.c | 49 ++
include/hw/pci/msix.h | 2 ++
include/monitor/hmp.h | 1 +
softmmu/qdev-monitor.c | 25 +
5 files changed, 90 insertions(+)
diff --git a/hmp
On 4/22/21 11:01 PM, Jason Wang wrote:
>
> 在 2021/4/23 下午12:47, Dongli Zhang 写道:
>> This is inspired by the discussion with Jason on below patchset.
>>
>> https://urldefense.com/v3/__https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg090
On 4/23/21 12:59 AM, Jason Wang wrote:
>
> 在 2021/4/23 下午12:47, Dongli Zhang 写道:
>> This patch is to add the HMP interface to dump MSI-X table and PBA, in
>> order to help diagnose the loss of IRQ issue in VM (e.g., if an MSI-X
>> vector is erroneously masked permanent
On 4/24/21 8:36 PM, Jason Wang wrote:
>
> 在 2021/4/24 上午1:32, Dongli Zhang 写道:
>>
>> On 4/23/21 12:59 AM, Jason Wang wrote:
>>> 在 2021/4/23 下午12:47, Dongli Zhang 写道:
>>>> This patch is to add the HMP interface to dump MSI-X table and PBA, in
>>>&
Hi Jason,
On 4/27/21 7:31 PM, Jason Wang wrote:
>
> 在 2021/4/27 下午4:53, Dr. David Alan Gilbert 写道:
>> * Dongli Zhang (dongli.zh...@oracle.com) wrote:
>>>
>>> On 4/22/21 11:01 PM, Jason Wang wrote:
>>>> 在 2021/4/23 下午12:47, Dongli Zhang 写道:
>>>
On 4/27/21 10:55 PM, Jason Wang wrote:
>
> 在 2021/4/28 下午1:10, Dongli Zhang 写道:
>> Hi Jason,
>>
>> On 4/27/21 7:31 PM, Jason Wang wrote:
>>> 在 2021/4/27 下午4:53, Dr. David Alan Gilbert 写道:
>>>> * Dongli Zhang (dongli.zh...@oracle.com) wrote:
>>
On 4/28/21 1:45 AM, Dr. David Alan Gilbert wrote:
> * Dongli Zhang (dongli.zh...@oracle.com) wrote:
>> Hi Jason,
>>
>> On 4/27/21 7:31 PM, Jason Wang wrote:
>>>
>>> 在 2021/4/27 下午4:53, Dr. David Alan Gilbert 写道:
>>>> * Dongli Zhang (dongli.zh
(e.g.,
vhost-scsi) from QEMU/host to VM, while the 'kick' is to kick the doorbell
on purpose by admin at QEMU/host side for a specific device.
Signed-off-by: Dongli Zhang
---
hmp-commands.hx| 14 ++
include/hw/qdev-core.h | 6 ++
include/
{
locked_pending = 0,
tail = 0
}
}
}
}
}
},
head = {
next = 0xa104ae40d360,
prev = 0xa104ae40d360
}
},
count = 31, -> eventfd incremented to 31 !!!
flags = 526336,
id = 26
}
Only the interface for vhost-scsi is implemented since this is RFC. I will
implement for other types (e.g., eventfd or MSI-X) if the RFC is reasonable.
Thank you very much!
Dongli Zhang
ents": { "dev": "/machine/peripheral/vscsi0",
"event": "kick",
"queue": 1 } }
Signed-off-by: Dongli Zhang
---
hw/virtio/vhost-scsi-pci.c | 10 ++
hw/virtio/virtio.c | 19 +++
include
On 1/18/21 8:59 AM, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
>> On Thu, Jan 14, 2021 at 04:27:28PM -0800, Dongli Zhang wrote:
>>> The virtio device/driver (e.g., vhost-scsi and indeed any device including
>>> e1000e) may han
Hi Markus,
On 7/14/21 2:42 AM, Markus Armbruster wrote:
> Dongli Zhang writes:
>
>> Hi Markus,
>>
>> On 7/13/21 10:46 PM, Markus Armbruster wrote:
>>> Dongli Zhang writes:
>>>
>>>> This patch is to add the HMP interface to dump MSI-X tab
+++
include/hw/pci/msix.h | 2 ++
include/hw/pci/pci.h | 3 ++
include/hw/virtio/virtio.h | 2 ++
include/monitor/hmp.h | 1 +
softmmu/qdev-monitor.c | 36 +++
10 files changed, 158 insertions(+)
Thank you very much!
Dongli Zhang
0x40d1 0x
MSI-X PBA
0 0 0 0 0 0 0
Since this is just for debugging by humans, provide the command only in
HMP, not in QMP.
Cc: Jason Wang
Cc: Joe Jin
Signed-off-by: Dongli Zhang
Acked-by: Dr. David Alan Gilbert
Acked-by: Jason Wang
---
Changed since v1/v2:
- Add msix_present() to
PCIDeviceClass->msix_info interface.
Cc: Jason Wang
Cc: Joe Jin
Suggested-by: Jason Wang
Signed-off-by: Dongli Zhang
Acked-by: Jason Wang
---
hmp-commands-info.hx | 7 ---
include/hw/pci/pci.h | 3 +++
softmmu/qdev-monitor.c | 11 +++
3 files changed, 18 insertions(+)
2: 3
queue 3: 4
queue 4: 5
queue 5: 6
Cc: Jason Wang
Cc: Joe Jin
Suggested-by: Jason Wang
Signed-off-by: Dongli Zhang
Acked-by: Jason Wang
---
hw/virtio/virtio-pci.c | 22 ++
hw/virtio/virtio.c | 10 ++
include/hw/virtio/virtio.h | 2 ++
3 files
May I get feedback for this bugfix?
So far the "info lapic " returns stale data and could not accurate reflect
the status in KVM.
Thank you very much!
Dongli Zhang
On 7/1/21 2:40 PM, Dongli Zhang wrote:
> While the default "info lapic" always synchronizes cpu sta
PCIDeviceClass->msix_info interface.
Cc: Jason Wang
Cc: Joe Jin
Suggested-by: Jason Wang
Signed-off-by: Dongli Zhang
---
hmp-commands-info.hx | 7 ---
include/hw/pci/pci.h | 3 +++
softmmu/qdev-monitor.c | 11 +++
3 files changed, 18 insertions(+), 3 deletions(-)
diff --gi
changed, 153 insertions(+)
Thank you very much!
Dongli Zhang
Wang
Cc: Joe Jin
Signed-off-by: Dongli Zhang
Acked-by: Dr. David Alan Gilbert
---
hmp-commands-info.hx | 13 +
hw/pci/msix.c | 63 ++
include/hw/pci/msix.h | 2 ++
include/monitor/hmp.h | 1 +
softmmu/qdev-monitor.c | 25
2: 3
queue 3: 4
queue 4: 5
queue 5: 6
Cc: Jason Wang
Cc: Joe Jin
Suggested-by: Jason Wang
Signed-off-by: Dongli Zhang
---
hw/virtio/virtio-pci.c | 22 ++
hw/virtio/virtio.c | 10 ++
include/hw/virtio/virtio.h | 2 ++
3 files changed, 34 insertions
>From source code, the 'devid' of x-remote-object should be one of devices
in remote QEMU process.
Signed-off-by: Dongli Zhang
Reviewed-by: Jagannathan Raman
---
Resend to be applied as trivial patch.
I have verified by reading the code and playing with below orchestrator.
https
On 7/13/21 1:59 PM, Michael S. Tsirkin wrote:
> On Mon, Jul 12, 2021 at 04:58:09PM -0700, Dongli Zhang wrote:
>> I have just rebased the v2 patchset on top of most recent qemu to resend.
>>
>> This patch is to introduce the new HMP command to dump the MSI-X table/PBA.
>
| 2 ++
include/monitor/hmp.h | 1 +
softmmu/qdev-monitor.c | 36 +++
10 files changed, 158 insertions(+)
Thank you very much!
Dongli Zhang
Wang
Cc: Joe Jin
Signed-off-by: Dongli Zhang
Acked-by: Dr. David Alan Gilbert
Acked-by: Jason Wang
---
Changed since v1/v2:
- Add msix_present() to pci-stub.c to avoid build error
hmp-commands-info.hx | 13 +
hw/pci/msix.c | 63
2: 3
queue 3: 4
queue 4: 5
queue 5: 6
Cc: Jason Wang
Cc: Joe Jin
Suggested-by: Jason Wang
Signed-off-by: Dongli Zhang
Acked-by: Jason Wang
---
hw/virtio/virtio-pci.c | 22 ++
hw/virtio/virtio.c | 10 ++
include/hw/virtio/virtio.h | 2 ++
3 files
PCIDeviceClass->msix_info interface.
Cc: Jason Wang
Cc: Joe Jin
Suggested-by: Jason Wang
Signed-off-by: Dongli Zhang
Acked-by: Jason Wang
---
hmp-commands-info.hx | 7 ---
include/hw/pci/pci.h | 3 +++
softmmu/qdev-monitor.c | 11 +++
3 files changed, 18 insertions(+)
Hi Markus,
On 7/13/21 10:46 PM, Markus Armbruster wrote:
> Dongli Zhang writes:
>
>> This patch is to add the HMP interface to dump MSI-X table and PBA, in
>> order to help diagnose the loss of IRQ issue in VM (e.g., if an MSI-X
>> vector is erroneously masked permanent
_dest & APIC_LOGDEST_XAPIC_ID);
> +g_string_append_printf(buf, "(cluster %u: id %u)",
> + s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
> + s->log_dest & APIC_LOGDEST_XAPIC_ID);
> }
&g
ent.
The cpu state should be synchronized when apic-id is available. Otherwise
the "info lapic " always returns stale data.
Cc: Joe Jin
Signed-off-by: Dongli Zhang
---
Changed since v1:
- I sent out wrong patch version in v1
target/i386/monitor.c | 5 +
1 file changed, 5 insertions
ent.
The cpu state should be synchronized when apic-id is available. Otherwise
the "info lapic " always returns stale data.
Cc: Joe Jin
Signed-off-by: Dongli Zhang
---
target/i386/monitor.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
Please ignore this patch. I sent out the wrong version without memory check.
I will re-send again.
Thank you very much!
Dongli Zhang
On 7/1/21 2:26 PM, Dongli Zhang wrote:
> While the default "info lapic" always synchronizes cpu state ...
>
> mon_get_cpu()
> -> m
ent.
The cpu state should be synchronized when apic-id is available. Otherwise
the "info lapic " always returns stale data.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- I sent out wrong patch version in v1
target/i386/monitor.c | 5 +
1 file changed, 5 insertions(+)
diff --
nly 2 queues
available /sys/block/sda/mq/
https://lore.kernel.org/lkml/1553682995-5682-1-git-send-email-dongli.zh...@oracle.com/
I am just curious how increasing the num_queues from 2 to 4 would double the
iops, while there are only 2 vcpus available...
Dongli Zhang
>
> In addition, It se
n-loop.c:512
#16 0x55a0beeb in main_loop () at vl.c:1970
#17 0x55a13230 in main (argc=15, argv=0x7fffe3a8,
envp=0x7fffe428) at vl.c:4604
Dongli Zhang
0:2:0:0: Unexpected response from lun 1 while scanning,
scan aborted
[0.540364] scsi host1: ata_piix
[0.540780] scsi host2: ata_piix
[0.702396] scsi 1:0:0:0: Direct-Access ATA QEMU HARDDISK2.5+
PQ: 0 ANSI: 5
When 'lun=1' is changed to 'lun=0', there is no issue.
Thank you very much!
Dongli Zhang
On 3/27/19 7:31 PM, Hannes Reinecke wrote:
> On 3/26/19 5:47 PM, Dongli Zhang wrote:
>> I am reporting an error that the scsi lun cannot initialize successfully
>> when I
>> am emulating megasas scsi controller with qemu.
>>
>> I am not sure if this is issue in
nto the VM kernel:
[...] Uhhuh. NMI received for unknown reason 30 on CPU 0.
To resolve these issues, we propose resetting AMD PMU registers during the
VM reset process
Dongli Zhang (7):
target/i386: disable PerfMonV2 when PERFCORE unavailable
target/i386/kvm: introduce 'pmu-cap-disabled&
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in cpuid when PERFCORE is disabled.
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: Dongli Zhang
---
target/
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
---
target/i386/cpu.h | 8 +++
target/i386/kvm/kvm.c | 156 +-
2 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.h b/t
, the meaning of has_pmu_version remains unchanged.
For AMD processors:
has_pmu_version == 1 corresponds to versions before AMD PerfMonV2.
has_pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 49 ---
1
re currently
supports only x86 hosts, as KVM_CAP_PMU_CAPABILITY is used exclusively for
x86 systems.
Signed-off-by: Dongli Zhang
---
Another previous solution to re-use '-cpu host,-pmu':
https://lore.kernel.org/all/20221119122901.2469-1-dongli.zh...@oracle.com/
accel/kvm/kvm-all.c
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
--
ode.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bugfix.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm
n only once for the first vCPU.
Additionally, the code extracted from kvm_x86_build_cpuid() is unrelated to
the process of building the CPUID.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 71 +++
1 file changed, 44 insertions(+), 27 deletions(-)
diff -
Hi Sandipan,
On 11/8/24 5:09 AM, Sandipan Das wrote:
> On 11/4/2024 3:10 PM, Dongli Zhang wrote:
[snip]
>> + * separate set of addresses for the selector and counter
>> + * registers. Additionally, the address of the next selector or
>> +
nction by other patches,
including the initialization of both Intel and AMD PMU infortmation (PerfMonV2).
Thank you very much!
Dongli Zhang
>
>> if (((env->cpuid_version >> 8)&0xF) >= 6
>> && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
>> (CPUID_MCE | CPUID_MCA)) {
>> --
>> 2.39.3
>>
Although the unsupported MSR write doesn't trigger any issue (thanks to
msrs_to_save_pmu[]), I agree this is the bug that I will address in v2.
Thanks to the reminder, indeed I have noticed another issue to be addressed in
v2: something unexpected may happen if we migrate from old KVM to new KVM
(assuming same QEMU versions).
Suppose one user never notice "-pmu" doesn't work on old AMD KVM, but still add
"-pmu" to QEMU command line.
old AMD KVM: "-pmu" doesn't take effect, due to the lack of
KVM_CAP_PMU_CAPABILITY.
new AMD KVM: "-pmu" takes effect.
After the migration, the vPMU won't work any longer from guest's perspective.
> implementation without pmu-cap-disabled (which was suggested before) to save
> guest-visible state during migration.
Yes, I am going to revert back to my previous solution with "-pmu".
Thanks everyone's suggestion on "-pmu" vs. "pmu-cap-disabled". To finalize the
decision helps move forward.
Would you mind clarify "without pmu-cap-disabled (which was suggested before) to
save guest-visible state during migration."?
Would you mean the compatibility issue between old QEMU version (without
"pmu-cap-disabled") and new QEMU version (with "pmu-cap-disabled")?
Thank you very much!
Dongli Zhang
ith PerfMonV2).
I will make it more readable in v2 following your suggestion.
Thank you very much!
Dongli Zhang
tatic int __init amd_core_pmu_init(void)
1404 {
1405 union cpuid_0x8022_ebx ebx;
1406 u64 even_ctr_mask = 0ULL;
1407 int i;
1408
1409 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
1410 return 0;
If you don't mind, I will send the v2 with your Suggested-by.
Thank you very much!
Dongli Zhang
Hi Zhao,
On 11/6/24 11:52 PM, Zhao Liu wrote:
> (+Dapang & Zide)
>
> Hi Dongli,
>
> On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote:
>> Date: Mon, 4 Nov 2024 01:40:17 -0800
>> From: Dongli Zhang
>> Subject: [PATCH 2/7] target/i386/kvm
Hi Maksim,
On 11/7/24 1:00 PM, Maksim Davydov wrote:
>
>
> On 11/4/24 12:40, Dongli Zhang wrote:
>> QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
>> and kvm_put_msrs() to restore them to KVM. However, there is no support for
>> A
5zZnDp1b1gVmO-DdpYxMvO1hlH9owAHV5UMT$
>
>
Thank you very much for the reminder!
Dongli Zhang
de)
>>>>
>>>> Hi Dongli,
>>>>
>>>> On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote:
>>>>> Date: Mon, 4 Nov 2024 01:40:17 -0800
>>>>> From: Dongli Zhang
>>>>> Subject: [PATCH 2/7] target/i386/kvm
age02
Signed-off-by: Dongli Zhang
---
hw/scsi/vhost-scsi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c
index 8039d13fd9..d3a260f6a7 100644
--- a/hw/scsi/vhost-scsi.c
+++ b/hw/scsi/vhost-scsi.c
@@ -359,6 +359,9 @@ static const Property v
, if kvm.enable_pmu=N.
In addition, return error when kvm.enable_pmu=N but the user wants to enable
vPMU.
Signed-off-by: Dongli Zhang
---
Changed since v2:
- Rework the code flow following Zhao's suggestion.
- Return error when:
(*kvm_enable_pmu == 'N' &&a
t; Zhaoxin (including vendor "__shanghai__" and "centaurhauls")'s PMU is
> compatible with Intel, so I have some advice for this patch.
>
> 在 2025/3/3 06:00, Dongli Zhang 写道:
>> [snip]
>> +
>> +static bool is_same_vendor(CPUX86State *env)
tdp_mmu? Or the legacy
perf-based vPMU is going to be purged from the most recent kernel?
If they can coexist, how about add property to QEMU control between
legacy/modern? i.e. by default use legacy and change to modern as default in the
future once the feature is stable.
Thank you very much!
Dongli
v3 patchset, it always follows the Intel path, if both guest and host are
Intel or Zhaoxin.
https://lore.kernel.org/qemu-devel/20250331013307.11937-9-dongli.zh...@oracle.com/
Thank you very much!
Dongli Zhang
try() instead of cpu_x86_cpuid(), because
CPUID has already been filled at this stage.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Still extract the code, but call them for all CPUs.
Changed since v2:
- Use cpuid_find_entry() instead of cpu_x86_cpuid().
- Didn't add Reviewed-by fr
: Gerd Hoffmann
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Add my Signed-off-by.
accel/kvm/kvm-all.c| 5 +
include/system/kvm.h | 1 +
target/arm/kvm.c | 5 +
target/i386/kvm/kvm.c | 5 +
target/loongarch/kvm/kvm.c | 5
kvm.enable_pmu value from the module sysfs to give a chance to
provide more information about vPMU enablement.
Signed-off-by: Dongli Zhang
---
Changed since v2:
- Rework the code flow following Zhao's suggestion.
- Return error when:
(*kvm_enable_pmu == 'N' && X86_CPU(cp
Hi Zhao,
On 4/10/25 1:21 AM, Zhao Liu wrote:
> On Sun, Mar 30, 2025 at 06:32:28PM -0700, Dongli Zhang wrote:
>> Date: Sun, 30 Mar 2025 18:32:28 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v3 09/10] target/i386/kvm: support perfmon-v2 for reset
>> X-Mailer: git-se
index = index - MSR_F15H_PERF_CTL0;
>> +if (index & 0x1) {
>> +env->msr_gp_counters[index] = msrs[i].data;
>> +} else {
>> +env->msr_gp_evtsel[index] = msrs[i].data;
>
> This msr_gp_evtsel[] array's size is 18:
>
> #define MAX_GP_COUNTERS(MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
>
> This formula is based on Intel's MSR, it's best to add a note that the
> current size also meets AMD's needs. (No need to adjust the size, as
> it will affect migration).
I will add a comment to target/i386/cpu.h, above the definition of
MAX_GP_COUNTERS.
Thank you very much!
Dongli Zhang
*
> + * KVM_PMU_CAP_DISABLE doesn't change the PMU
> + * behavior on Intel platform because current "pmu" property
> works
> + * as expected.
> + */
> +if ((pmu_cap & KVM_PMU_CAP_DISABLE)) {
> +ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PMU_CAPABILITY, 0,
> +KVM_PMU_CAP_DISABLE);
> +if (ret < 0) {
> +error_setg_errno(errp, -ret,
> + "Failed to set KVM_PMU_CAP_DISABLE");
> +return ret;
> }
> }
> }
>
Thank you very much! I will split based on (enable_pmu) and (!enable_pmu)
following your suggestion.
Dongli Zhang
try() instead of cpu_x86_cpuid(), because
CPUID has already been filled at this stage.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v1:
- Still extract the code, but call them for all CPUs.
Changed since v2:
- Use cpuid_find_entry() instead of cpu_x86_cpuid().
- Didn't
nable_pmu, NULL, NULL)) {
> -if (*kvm_enable_pmu == 'N' && X86_CPU(cpu)->enable_pmu) {
> -error_setg(errp, "Failed to enable PMU since "
> +if (*kvm_enable_pmu == 'N') {
> +warn_report("
any CPUID bit to indicate PMU
availability.
To address this, KVM_CAP_PMU_CAPABILITY is used to set KVM_PMU_CAP_DISABLE
when "-pmu" is configured.
Signed-off-by: Dongli Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Zhao Liu
---
Changed since v1:
- Switch back to the initial implementation
, the meaning of pmu_version remains unchanged.
For AMD processors:
pmu_version == 1 corresponds to versions before AMD PerfMonV2.
pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
Reviewed-by: Dapeng Mi
Reviewed-by: Zhao Liu
---
Changed since v2:
- Change
omment.
- Bring back global static variable 'kvm_pmu_disabled' read from
/sys/module/kvm/parameters/enable_pmu.
Zhao Liu (1):
i386/cpu: Consolidate the helper to get Host's vendor [Don't merge]
Xiaoyao Li (1):
kvm: Introduce kvm_arch_pre_create_vcpu()
Dongli Zhang (9)
ting PMC. This approach is true since Linux kernel
commit 68fb4757e867 ("KVM: x86/pmu: Defer reprogram_counter() to
kvm_pmu_handle_event"), that is, v6.2.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bug
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in CPUID when PERFCORE is disabled.
Suggested-by: Zhao Liu
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: D
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
AMD64_NUM_COUNTERS (suggested by Sandipan Das).
- Use "AMD64_NUM_COUNTERS_COR
Acked-by: Gerd Hoffmann
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Add my Signed-off-by.
Changed since v3:
- Pick new reviewed version from:
https://lore.kernel.org/all/20250401130205.2198253-8-xiaoyao...@intel.com/
I have fixed
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
Re
From: Zhao Liu
Extend host_cpu_vendor_fms() to help more cases to get Host's vendor
information.
Cc: Dongli Zhang
Signed-off-by: Zhao Liu
---
This patch is already queued by Paolo.
https://lore.kernel.org/all/20250410075619.145792-1-zhao1@intel.com/
I don't need to add my Sig
g on env->features[] in future patches.
Suggested-by: Zhao Liu
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- No need to check "kvm_enabled() && IS_AMD_CPU(env)".
target/i386/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cp
Ping?
Any chance to accept this property? It is acked by Stefano Garzarella.
It helped me test vhost-scsi event queue and live migration recently.
https://lore.kernel.org/all/20250403063028.16045-9-dongli.zh...@oracle.com/
Thank you very much!
Dongli Zhang
On 2/11/25 8:26 AM, Stefano
Would you mind suggesting any next steps on this issue?
1. Increase maximum size for "etc/acpi/rsdp", or
2. Remove host page size based alignment, and then fix any further live
migration issue?
Thank you very much!
Dongli Zhang
On 1/31/23 1:17 AM, Feng Sun wrote:
> Michael S. Tsi
Hi Zhao,
On 4/25/25 1:28 AM, Zhao Liu wrote:
> On Wed, Apr 16, 2025 at 02:52:26PM -0700, Dongli Zhang wrote:
>> Date: Wed, 16 Apr 2025 14:52:26 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper
>> to get Host
comment.
- Bring back global static variable 'kvm_pmu_disabled' read from
/sys/module/kvm/parameters/enable_pmu.
Changed since v4:
- Re-base on top of most recent mainline QEMU.
- Add more Reviewed-by.
- All patches are reviewed.
Xiaoyao Li (1):
kvm: Introduce kvm_arch
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
Re
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
Reviewed-by: Sandipan Das
---
Changed since v1:
- Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
AMD64_NUM_COUNTERS
kvm.enable_pmu value from the module sysfs to give a chance to
provide more information about vPMU enablement.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Rework the code flow following Zhao's suggestion.
- Return error when:
(*kvm_enable_pmu == 'N'
try() instead of cpu_x86_cpuid(), because
CPUID has already been filled at this stage.
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v1:
- Still extract the code, but call them for all CPUs.
Changed since v2:
- Use cpuid_find_entry() instead of cpu_x86_cpuid().
- Didn't
g on env->features[] in future patches.
Suggested-by: Zhao Liu
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
Reviewed-by: Sandipan Das
---
Changed since v2:
- No need to check "kvm_enabled() && IS_AMD_CPU(env)".
Changed since v4:
- Add Reviewed-by from Sandipan.
target
any CPUID bit to indicate PMU
availability.
To address this, KVM_CAP_PMU_CAPABILITY is used to set KVM_PMU_CAP_DISABLE
when "-pmu" is configured.
Signed-off-by: Dongli Zhang
Reviewed-by: Xiaoyao Li
Reviewed-by: Zhao Liu
---
Changed since v1:
- Switch back to the initial implementation
, the meaning of pmu_version remains unchanged.
For AMD processors:
pmu_version == 1 corresponds to versions before AMD PerfMonV2.
pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
Reviewed-by: Dapeng Mi
Reviewed-by: Zhao Liu
---
Changed since v2:
- Change
idge perf ctrs = 0x0 (0)
number of available UMC PMCs = 0x0 (0)
active UMCs bitmask = 0x0
Disable PerfMonV2 in CPUID when PERFCORE is disabled.
Suggested-by: Zhao Liu
Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit")
Signed-off-by: D
Acked-by: Gerd Hoffmann
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Dongli Zhang
Reviewed-by: Zhao Liu
---
Changed since v2:
- Add my Signed-off-by.
Changed since v3:
- Pick new reviewed version from:
https://lore.kernel.org/all/20250401130205.2198253-8-xiaoyao...@intel.com/
I have fixed
ting PMC. This approach is true since Linux kernel
commit 68fb4757e867 ("KVM: x86/pmu: Defer reprogram_counter() to
kvm_pmu_handle_event"), that is, v6.2.
No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm:
migrate vPMU state"), because this isn't a bug
Hi Zhao,
On 4/10/25 2:45 AM, Zhao Liu wrote:
> On Sun, Mar 30, 2025 at 06:32:29PM -0700, Dongli Zhang wrote:
>> Date: Sun, 30 Mar 2025 18:32:29 -0700
>> From: Dongli Zhang
>> Subject: [PATCH v3 10/10] target/i386/kvm: don't stop Intel PMU counters
>> X-Mailer:
inux.git/commit/?id=c52ffadc65e28ab461fd055e9991e8d8106a0056
David Woodhouse has a patchset related to kvmclock and live migration.
[RFC PATCH v3 00/21] Cleaning up the KVM clock mess
https://lore.kernel.org/all/20240522001817.619072-1-dw...@infradead.org/
Maciej also fixed a similar clock unsta
sues, we propose resetting AMD PMU registers during the
VM reset process.
Signed-off-by: Dongli Zhang
---
Changed since v1:
- Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using
AMD64_NUM_COUNTERS (suggested by Sandipan Das).
- Use "AMD64_NUM_COUNTE
tus.
- MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use
env->msr_global_ctrl.
- MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
both use env->msr_global_ovf_ctrl.
No changes are needed for vmstate_msr_architectural_pmu or
pmu_enable_needed().
Signed-off-by: Dongli Zhang
--
uot;-pmu" but not a global "pmu-cap-disabled" for KVM_PMU_CAP_DISABLE.
- Also use sysfs kvm.enable_pmu=N to determine if PMU is supported.
- Some changes to PMU register limit calculation.
Xiaoyao Li (1):
kvm: Introduce kvm_arch_pre_create_vcpu()
Dongli Zhang (9):
target/i386:
The initialization of 'has_architectural_pmu_version',
'num_architectural_pmu_gp_counters', and
'num_architectural_pmu_fixed_counters' is unrelated to the process of
building the CPUID.
Extract them out of kvm_x86_build_cpuid().
No functional change.
Signed-off
g on env->features[] in future patches.
Suggested-by: Zhao Liu
Signed-off-by: Dongli Zhang
---
target/i386/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b6d6167910..61a671028a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
, the meaning of has_pmu_version remains unchanged.
For AMD processors:
has_pmu_version == 1 corresponds to versions before AMD PerfMonV2.
has_pmu_version == 2 corresponds to AMD PerfMonV2.
Signed-off-by: Dongli Zhang
---
target/i386/kvm/kvm.c | 49 ---
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