> -Original Message-
> From: qemu-devel-bounces+sidneym=quicinc@nongnu.org devel-bounces+sidneym=quicinc@nongnu.org> On Behalf Of Sid
> Manning
> Sent: Thursday, January 5, 2023 7:08 PM
> To: 'Richard Henderson' ; qemu-
> de...@nongnu.org
>
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, January 26, 2023 3:48 PM
> To: Sid Manning ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; Mark Burton ; Alex
> Bennée
> Subject: Re: ARM: ptw.c:S1_ptw_translate
>
> WARNING: This email
There is an assert in translator_access that I hit while running on a version
of QEMU integrated into a Virtual Platform.
Since this function can return null anyway I tried the following experiment:
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -172,7 +172,9 @@ static void *transl
Currently when I attach a debugger (lldb) to my qemu session all of the output
goes to the shell running qemu not to the debugger. Fixing this meant that I
needed to point the semi-hosting output to the gdb chardev. I started qemu
like this:
-s -S -semihosting-config target=auto,chardev=ch0 -
> -Original Message-
> From: Alex Bennée
> Sent: Thursday, October 21, 2021 9:52 AM
> To: Philippe Mathieu-Daudé
> Cc: Sid Manning ; Marc-André Lureau
> ; Paolo Bonzini ;
> qemu-devel@nongnu.org
> Subject: Re: [gdbstub] redirecting qemu console output to a deb
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, January 31, 2023 11:46 PM
> To: Sid Manning ; qemu-devel@nongnu.org
> Cc: Mark Burton ; Brian Cain
> ; Matheus Bernardino
>
> Subject: Re: accel/tcg/translator.c question about translator_access
> -Original Message-
> From: Jørgen Hansen
> Sent: Tuesday, February 7, 2023 9:03 AM
> To: Richard Henderson ; qemu-
> de...@nongnu.org
> Cc: Sid Manning ; Mark Burton
> ; Brian Cain ; Matheus
> Bernardino ; Ajay Joshi
>
> Subject: Re: [PATCH 1/1] accel/tc
ptw.c:S1_ptw_translate
After migrating to v7.2.0, an issue was found where we were not getting the
correct virtual address from a load insn. Reading the address used in the load
insn from the debugger resulted in the execution of the insn getting the
correct value but simply stepping over the
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, January 4, 2023 11:42 PM
> To: Sid Manning ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; Mark Burton
> Subject: Re: ARM: ptw.c:S1_ptw_translate
>
> WARNING: This email originated from outsid
Hi Taylor,
I ran into an issue when a packet, not executed out of ram
(get_page_addr_code_hostp returns -1, see translate-all.c) contains a fault.
This packet is an example:
{
p0 = cmp.eq(r6,#0x6)
if (p0.new) jump:t pass
memw(##0xf200) = r6
}
The above packet should always jump t
I’m looking at a testcase failure when my target uses 64bit time in msg.h
(struct msqid_ds). I’ve been able to get around this but changing
target_msqid_ds like so:
@@ -3900,18 +3901,9 @@ static inline abi_long do_semop(int semid, abi_long ptr,
unsigned nsops)
struct target_msqid_ds
{
st
> -Original Message-
> From: Laurent Vivier
> Sent: Wednesday, May 27, 2020 11:23 AM
> To: Sid Manning ; qemu-devel@nongnu.org
> Subject: [EXT] Re: linux-user - time64 question
>
> Le 05/05/2020 à 23:38, Sid Manning a écrit :
> > I’m looking at a testcase failur
> -Original Message-
> From: Brian Cain
> Sent: Monday, July 19, 2021 8:40 AM
> To: Rob Landley ; Taylor Simpson
> ; qemu-devel@nongnu.org; Sid Manning
>
> Cc: a...@rev.ng; peter.mayd...@linaro.org; richard.hender...@linaro.org;
> phi...@redhat.com
> Subject:
kvm_flush_coalesced_mmio_buffer explicitly checks for this to
be non-null. Since kvm_init_vcpu sets this as an offset from the mapped
cpu->kvm_run it should be reset to NULL after kvm_run is unmapped.
Signed-off-by: Sid Manning
---
accel/kvm/kvm-all.c | 2 ++
1 file changed, 2 inserti
renced
by kvm_flush_coalesced_mmio_buffer.
Sid Manning (1):
accel/kvm: set coalesced_mmio_ring to NULL after kvm_run is unmapped
accel/kvm/kvm-all.c | 2 ++
1 file changed, 2 insertions(+)
--
2.34.1
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 08/38] target/hexagon: Add guest, system reg number
> defs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachm
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 30/38] target/hexagon: Add a TLB count property
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 28/38] target/hexagon: Initialize htid, modectl regs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 33/38] target/hexagon: Add gdb support for sys regs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
> -Original Message-
> From: Sid Manning
> Sent: Wednesday, March 12, 2025 2:10 PM
> To: ltaylorsimp...@gmail.com; 'Brian Cain'
> ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
> (QUIC) ; a...@rev.ng; a.
Marco Liebel
> (QUIC) ; ltaylorsimp...@gmail.com;
> alex.ben...@linaro.org; Mark Burton (QUIC)
> ; Sid Manning ; Brian
> Cain
> Subject: [PATCH 31/38] target/hexagon: Add {TLB,k0}lock, cause code,
> wait_next_pc
>
> From: Brian Cain
>
> {TLB,k0}lock counts are used to r
gmail.com;
> alex.ben...@linaro.org; Mark Burton (QUIC)
> ; Sid Manning ; Brian
> Cain ; Michael Lambert
> Subject: Re: [PATCH 34/38] target/hexagon: Add initial MMU model
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 01/39] target/hexagon: Implement ciad helper
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 05/39] target/hexagon: Implement modify SSR
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
...@rev.ng; Marco Liebel (QUIC)
> ; alex.ben...@linaro.org; Mark Burton (QUIC)
> ; Sid Manning ; Brian
> Cain
> Subject: Re: [PATCH 28/38] target/hexagon: Initialize htid, modectl regs
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any link
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 22/39] target/hexagon: Implement setprio, resched
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, March 20, 2025 10:34 AM
> To: Sid Manning ; ltaylorsimp...@gmail.com;
> 'Philippe Mathieu-Daudé' ; 'Brian Cain'
> ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ;
>
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain ; 'Mike Lambert'
>
> Subject: RE: [PATCH 17/39] target/hexagon: Implement software interrupt
>
> WARNING: This email originated from outside of Qualcomm. Please be w
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