> -----Original Message----- > From: ltaylorsimp...@gmail.com <ltaylorsimp...@gmail.com> > Sent: Thursday, March 20, 2025 2:45 PM > To: 'Brian Cain' <brian.c...@oss.qualcomm.com>; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino > (QUIC) <quic_mathb...@quicinc.com>; a...@rev.ng; a...@rev.ng; Marco > Liebel (QUIC) <quic_mlie...@quicinc.com>; alex.ben...@linaro.org; Mark > Burton (QUIC) <quic_mbur...@quicinc.com>; Sid Manning > <sidn...@quicinc.com>; Brian Cain <bc...@quicinc.com> > Subject: RE: [PATCH 22/39] target/hexagon: Implement setprio, resched > > WARNING: This email originated from outside of Qualcomm. Please be wary > of any links or attachments, and do not enable macros. > > > -----Original Message----- > > From: Brian Cain <brian.c...@oss.qualcomm.com> > > Sent: Friday, February 28, 2025 11:28 PM > > To: qemu-devel@nongnu.org > > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; > a...@rev.ng; > > quic_mlie...@quicinc.com; ltaylorsimp...@gmail.com; > > alex.ben...@linaro.org; quic_mbur...@quicinc.com; > sidn...@quicinc.com; > > Brian Cain <bc...@quicinc.com> > > Subject: [PATCH 22/39] target/hexagon: Implement setprio, resched > > > > From: Brian Cain <bc...@quicinc.com> > > > > The hardware-assisted scheduler helps manage tasks on the run queue > > and interrupt steering. > > > > This instruction is defined in the Qualcomm Hexagon V71 Programmer's > > Reference Manual - > https://docs.qualcomm.com/bundle/publicresource/80- > > N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf > > See ยง11.9.2 SYSTEM MONITOR. > > See earlier discussion on references to documents. > > > > > Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com> > > --- > > target/hexagon/op_helper.c | 65 > > ++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 65 insertions(+) > > > > diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c > > index 0dce133d3a..d0dc4afac7 100644 > > --- a/target/hexagon/op_helper.c > > +++ b/target/hexagon/op_helper.c > > @@ -1465,6 +1465,57 @@ void HELPER(stop)(CPUHexagonState *env) > > hexagon_stop_thread(env); > > } > > > > +static inline QEMU_ALWAYS_INLINE void resched(CPUHexagonState > *env) > > { > > + uint32_t schedcfg; > > + uint32_t schedcfg_en; > > + int int_number; > > + CPUState *cs; > > + uint32_t lowest_th_prio = 0; /* 0 is highest prio */ > > + uint32_t bestwait_reg; > > + uint32_t best_prio; > > + > > + BQL_LOCK_GUARD(); > > + qemu_log_mask(CPU_LOG_INT, "%s: check resched\n", __func__); > > + schedcfg = arch_get_system_reg(env, HEX_SREG_SCHEDCFG); > > + schedcfg_en = GET_FIELD(SCHEDCFG_EN, schedcfg); > > + int_number = GET_FIELD(SCHEDCFG_INTNO, schedcfg); > > + > > + if (!schedcfg_en) { > > + return; > > + } > > + > > + CPU_FOREACH(cs) { > > + HexagonCPU *thread = HEXAGON_CPU(cs); > > + CPUHexagonState *thread_env = &(thread->env); > > + uint32_t th_prio = GET_FIELD( > > + STID_PRIO, arch_get_system_reg(thread_env, HEX_SREG_STID)); > > + if (!hexagon_thread_is_enabled(thread_env)) { > > + continue; > > + } > > + > > + lowest_th_prio = (lowest_th_prio > th_prio) > > + ? lowest_th_prio > > + : th_prio; > > + } > > + > > + bestwait_reg = arch_get_system_reg(env, HEX_SREG_BESTWAIT); > > + best_prio = GET_FIELD(BESTWAIT_PRIO, bestwait_reg); > > + > > + /* > > + * If the lowest priority thread is lower priority than the > > + * value in the BESTWAIT register, we must raise the reschedule > > + * interrupt on the lowest priority thread. > > + */ > > + if (lowest_th_prio > best_prio) { > > + qemu_log_mask(CPU_LOG_INT, > > + "%s: raising resched int %d, cur PC 0x" TARGET_FMT_lx "\n", > > + __func__, int_number, arch_get_thread_reg(env, > HEX_REG_PC)); > > + SET_SYSTEM_FIELD(env, HEX_SREG_BESTWAIT, BESTWAIT_PRIO, > > 0x1ff); > > What is the significance of 0x1ff? The field is 10 bits, so this isn't > setting all > the bits. > Should this be lowest_th_prio? [Sid Manning]
Hi Taylor, The value 0x1ff is correct but it does look like BESTWAIT_PRIO is not, it should be 9 not 10 target/hexagon/reg_fields_def.h.inc It looks like it was added in "PATCH 19/38 target/hexagon: Define register fields for system regs" I will make a fixup to that patch and correct the value. > > > + hex_raise_interrupts(env, 1 << int_number, CPU_INTERRUPT_SWI); > > + } > > +} > > + >
