From: Petar Jovanovic
helper_shilo has not been shifting an accumulator value correctly for negative
values in 'shift' field. Minor optimization for shift=0 case.
This change also adds tests that will trigger issue and check for regressions.
Signed-off-by: Petar Jovanovic
---
t
From: Petar Jovanovic
helper_shilo has not been shifting an accumulator value correctly for negative
values in 'shift' field. Minor optimization for shift=0 case.
This change also adds tests that will trigger issue and check for regressions.
Signed-off-by: Petar Jovanovic
---
t
From: Petar Jovanovic
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in
the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32
these bits must be written as zero, and return zero on read.
The change fixes writes (WRDSP) and reads (RDDSP) to the
From: Petar Jovanovic
The change removes some unnecessary and incorrect code for EXTR_S.H.
Further, it corrects the mask for shift value in the EXTR_ instructions. It also
extends the existing tests so they trigger the issues corrected with the change.
Signed-off-by: Petar Jovanovic
From: Petar Jovanovic
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectly
defines halfword vector elements as unsigned values. This results in wrong
output which is not triggered in the tests as they also follow this logic.
Signed-off-by: Petar Jovanovic
---
target
From: Petar Jovanovic
The change corrects sign-related issue with MULQ_S.PH. It also includes
extension to the already existing test which will trigger the issue.
Signed-off-by: Petar Jovanovic
---
target-mips/dsp_helper.c|2 +-
tests/tcg/mips/mips32-dspr2/mulq_s_ph.c
From: Petar Jovanovic
Correct sign-propagation before multiplication in MULQ_W helper.
The change also fixes previously incorrect expected values in the
tests for MULQ_RS.W and MULQ_S.W.
Signed-off-by: Petar Jovanovic
---
target-mips/dsp_helper.c|2 +-
tests/tcg/mips
ping
http://patchwork.ozlabs.org/patch/218695/
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Wednesday, February 06, 2013 6:05 PM
To: qemu-devel@nongnu.org
Cc: Jovanovic, Petar; aurel...@aurel32.net
Subject: [PATCH] target-mips: fix for incorrect
; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH] target-mips: fix for sign-issue in MULQ_W
helper
On 2013-02-07 10:36, Petar Jovanovic wrote:
> From: Petar Jovanovic
>
> Correct sign-propagation before multiplication in MULQ_W helper.
> The change also fixes previously incorr
From: Petar Jovanovic
The previous implementation incorrectly used same macro to detect overflow
for addition and subtraction. This patch makes distinction between these
two, and creates separate macros. The affected routines are changed
accordingly.
This change also includes additions to the
From: Petar Jovanovic
Fix for rndrashift_short_acc to set correct value to higher 64 bits.
This change also corrects conditions when bit 23 of the DSPControl register
is set.
The existing test files have been extended with several examples that
trigger the issues. One bug/example in the test
From: Petar Jovanovic
Previous implementation has failed to take into account different value of
SOCK_NONBLOCK on target (MIPS) and host, and existence of SOCK_CLOEXEC.
The same conversion has to be applied both for do_socket and do_socketpair,
so the code has been isolated in a static inline
ping
http://patchwork.ozlabs.org/patch/232770/
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Monday, April 01, 2013 5:49 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; riku.voi...@linaro.org; aurel...@aurel32.net;
r...@twiddle.net; blauwir
From: Petar Jovanovic
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format.
Otherwise, the results are unpredictable. Once the operands were corrected
in the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became
visible.
This change corrects the tests for MAQ_SA_W.PHL
There is a typo in the subject, it should say:
"target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHR"
Petar
____
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Monday, April 15, 2013 1:54 PM
To: qemu-devel@nongnu.org
Cc: Petar
+ qemu-triv...@nongnu.org
ping
From: Petar Jovanovic
Sent: Monday, April 08, 2013 8:31 PM
To: Peter Maydell; Petar Jovanovic
Cc: qemu-devel@nongnu.org; riku.voi...@linaro.org
Subject: RE: [Qemu-devel] [PATCH] linux-user: change do_semop to return target
Thanks Aurelien for your comments.
What others think? Can we submit this version of the patch? Riku? Richard, Blue?
Petar
From: Aurelien Jarno [aurel...@aurel32.net]
Sent: Monday, April 15, 2013 3:47 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar
ping
http://patchwork.ozlabs.org/patch/353815/
From: Aurelien Jarno [aurel...@aurel32.net]
Sent: Friday, May 30, 2014 10:02 AM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar Jovanovic; afaer...@suse.de; r...@twiddle.net
Subject: Re: [v4 PATCH] target
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This regis
Hi Leon,
thanks for spotting that. Done in v5.
Regards,
Petar
From: Leon Alrae
Sent: Wednesday, June 18, 2014 4:53 PM
To: Petar Jovanovic; Aurelien Jarno; Petar Jovanovic
Cc: r...@twiddle.net; qemu-devel@nongnu.org; afaer...@suse.de
Subject: Re: [Qemu
er [afaer...@suse.de]
Sent: Wednesday, June 18, 2014 5:21 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: r...@twiddle.net; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [v4 PATCH] target-mips: implement UserLocal Register
Am 29.05.2014 19:36, schrieb Petar Jovanovic:
> From: P
ping
Can somebody submit these for 1.6?
Thank you.
Regards,
Petar
__
From: Petar Jovanovic
Sent: Monday, July 22, 2013 10:51 AM
To: Richard Henderson; Petar Jovanovic
Cc: qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [PATCH v2] target-mips: fix
ping
Can somebody submit these for 1.6?
Thank you.
Regards,
Petar
From: Petar Jovanovic
Sent: Monday, July 22, 2013 10:52 AM
To: Richard Henderson
Cc: Petar Jovanovic; qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [Qemu-devel] [PATCH] target
Will there be an update to this patch?
It would be nice to see this in for 1.6.
As of fp64 mode for o32/Rev2, it does not have to be resolved now.
Regards,
Petar
On Sun, 9 Jun 2013, Thomas Schwinge wrote:
> In my reading of the relevant documents, the latter change is not correct
> for o32, and
From: Petar Jovanovic
Multiplication of two fractional word elements is not correct when sign
extension/promotion is needed. This change fixes it by adding correct
casts from unsigned to signed values.
In addition, the tests (dpaq_sa_l_w.c and dpsq_sa_l_w.c) have been extended
to trigger the
From: Petar Jovanovic
Five tests files for DSP instructions had wrong expected values in the tests.
This change fixes this, and this has been cross-checked by running the same
test binaries on Malta 74K board.
Signed-off-by: Petar Jovanovic
---
tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c
This is a small series of two patches. One expands the number of arguments
for gen_mfc0(), gen_mtc0(), gen_dmfc0(), and gen_dmtc0(), and the second
patch actually implements the register and access to it.
Regards,
Petar
Petar Jovanovic (2):
target-mips: pass CPUMIPSState to gen_mfc0/mtc0/dmfc0
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This regis
From: Petar Jovanovic
Add CPUMIPSState in gen_mfc0/mtc0/dmfc0/dmtc0, as it will be used in the
next patch that implements UserLocal register and access to it.
Signed-off-by: Petar Jovanovic
---
target-mips/translate.c | 44
1 file changed, 24
From: Petar Jovanovic
Previous implementation presumed that FPU registers are 64-bit and are
working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not
set, it does load/store from the odd numbered register pair.
Patch by Matthew Fortune.
Signed-off-by: Matthew Fortune
Signed
From: Petar Jovanovic
Flags NONBLOCK and CLOEXEC can have different values on the host and the
guest, so set correct host values before calling accept4().
This fixes several issues with accept4 system call and user-mode of QEMU.
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c | 13
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Monday, March 31, 2014 5:19 PM
To: Petar Jovanovic
Cc: QEMU Developers; Riku Voipio; Petar Jovanovic
Subject: Re: [Qemu-devel] [PATCH] linux-user: pass correct host flags to
accept4()
On 31 March 2014
From: Petar Jovanovic
Flags NONBLOCK and CLOEXEC can have different values on the host and the
guest, so set correct host values before calling accept4().
This fixes several issues with accept4 system call and user-mode of QEMU.
Signed-off-by: Petar Jovanovic
---
v2:
- use
From: Petar Jovanovic
Implementations of system calls getrusage and wait4 have not previously
handled correctly cases when incorrect address of struct rusage is
passed.
This change makes sure return values are correctly set for these cases.
Signed-off-by: Petar Jovanovic
---
linux-user
ping
+cc: qemu-devel@nongnu.org
From: Petar Jovanovic
Sent: Tuesday, December 10, 2013 10:32 AM
To: qemu-stable [qemu-sta...@nongnu.org]
Subject: backport three changes for v1.7.1
Can someone cherry-pick these three changes and put it into the 1.7 stable
From: Petar Jovanovic
This change corrects and simplifies how discard is calculated for shift
left logical vector instructions. It is used to detect overflow and set bit
22 in the DSPControl register.
The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases
that expose
ping
http://patchwork.ozlabs.org/patch/232770/
From: Petar Jovanovic
Sent: Tuesday, April 23, 2013 2:15 AM
To: Aurelien Jarno; Petar Jovanovic
Cc: qemu-devel@nongnu.org; riku.voi...@linaro.org; r...@twiddle.net;
blauwir...@gmail.com
Subject: RE: [PATCH v2
From: Andreas Färber [afaer...@suse.de]
Sent: Monday, April 29, 2013 4:56 PM
To: Petar Jovanovic
Cc: Aurelien Jarno; Petar Jovanovic; blauwir...@gmail.com;
riku.voi...@linaro.org; qemu-devel@nongnu.org; r...@twiddle.net; Alexander Graf
Subject: Re: [Qemu-devel] [PATCH v2
ping
http://patchwork.ozlabs.org/patch/232770/
From: Petar Jovanovic
Sent: Tuesday, April 30, 2013 3:20 AM
To: Andreas Färber
Cc: Aurelien Jarno; Petar Jovanovic; blauwir...@gmail.com;
riku.voi...@linaro.org; qemu-devel@nongnu.org; r...@twiddle.net
From: Petar Jovanovic
The emulator needs to check in hflags if DSP unit has been turned off before
it generates code for MUL_PH, MUL_S_PH, MULQ_S_W, and MULQ_RS_W.
Signed-off-by: Petar Jovanovic
---
target-mips/translate.c |1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips
From: Petar Jovanovic
This is a small follow-up change to "fix incorrect behaviour for INSV".
It includes two minor modifications:
- sizefilter is constant so it can be moved inside of the block,
- (int64_t)0x01 is replaced with 1LL for ease of reading.
No functional change.
Sig
True. Nice catch. This will simplify this section even more.
I will send an updated patch with this change included.
Petar
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Thursday, May 09, 2013 7:54 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org
From: Petar Jovanovic
This is a small follow-up change to "fix incorrect behaviour for INSV".
It includes two minor modifications:
- sizefilter is constant so it can be moved inside of the block,
- several lines of the code are replaced with a call to deposit64.
No functional chang
From: Petar Jovanovic
The mask for EXTP instruction when size=31 has not been correctly
calculated.
The test (mips32-dsp/extp.c) has been extended to include the case that
triggers the issue.
Signed-off-by: Petar Jovanovic
---
target-mips/dsp_helper.c |3 +--
tests/tcg/mips
From: Petar Jovanovic
This change makes sure that modifications of pos field in the DSPControl
register do not trash other bits in the register. This bug can be triggered
with the additional test case in mips32-dsp/extpdp.c in this commit.
In addition to this, this change corrects incorrect
From: Petar Jovanovic
First we need to clear the bit and then we set the given value.
Instruction ADDSC sets the bit and instruction ADDWC uses this bit.
Signed-off-by: Petar Jovanovic
---
target-mips/dsp_helper.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a
From: Aurelien Jarno [aurel...@aurel32.net]
Sent: Friday, May 17, 2013 7:34 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar Jovanovic
Subject: Re: [PATCH 2/2] target-mips: fix EXTPDP and setting up pos field in
the DSPControl reg
I am not sure it
From: Petar Jovanovic
This change makes sure that modifications of pos field in the DSPControl
register do not trash other bits in the register. This bug can be triggered
with the additional test case in mips32-dsp/extpdp.c in this commit.
In addition to this, this change corrects incorrect
From: Petar Jovanovic
This change makes sure that modifications of pos field in the DSPControl
register do not trash other bits in the register. This bug can be triggered
with the additional test case in mips32-dsp/extpdp.c in this commit.
In addition to this, this change corrects incorrect
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Friday, May 17, 2013 8:01 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: fix EXTPDP and setting up
pos field
From: Petar Jovanovic
This change corrects rounding and saturation of Q31 fractional value in
mipsdsp_trunc16_sat16_round(). Overflow detection was incorrect for the
corner case for PRECRQ_RS.PH, and this test case is also part of the change.
Signed-off-by: Petar Jovanovic
---
target-mips
ping
From: Petar Jovanovic
Sent: Wednesday, May 08, 2013 1:16 AM
To: riku.voi...@linaro.org; qemu-devel@nongnu.org
Cc: Aurelien Jarno; Petar Jovanovic; blauwir...@gmail.com; r...@twiddle.net;
Alexander Graf; Andreas Färber
Subject: RE: [Qemu-devel] [PATCH
From: Petar Jovanovic
Multiplication of Q15 fractional halfword vectors was incorrect in the
previous implementation of mipsdsp_rndq15_mul_q15_q15. It failed to take
element signs into account. This change fixes it, and it adds a test case
for it.
The change also removes unnecessary cast in the
me
only. Sorry!
> You probably wanted to say:
> git://github.com/petar-jovanovic/qemu.git mips-ufrp
I should have written that, yes.
Thanks.
Regards,
Petar
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Thursday, February 13, 2014 3:59 PM
T
From: Andreas Färber [afaer...@suse.de]
Sent: Thursday, February 13, 2014 5:11 PM
To: Peter Maydell; Petar Jovanovic
Cc: QEMU Developers; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for
MIPS32R5
From: Petar Jovanovic
Exception with break instruction has not been correctly propagated as
SIGTRAP. This resolves crash issues with examples that use break
instruction on MIPS.
Signed-off-by: Petar Jovanovic
---
linux-user/main.c |4
1 file changed, 4 insertions(+)
diff --git a
gards,
Petar
From: Andreas Färber [afaer...@suse.de]
Sent: Friday, February 28, 2014 4:30 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: riku.voi...@linaro.org; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH] linux-user: correct handling of break
exception
From: Petar Jovanovic
On success, sigtimedwait() returns a signal number that needs to be
translated from a host value to a target value.
This change also fixes issues with sigwait (that is implemented using
sigtimedwait()).
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c | 16
: Michael Roth
Cc: qemu-devel@nongnu.org; qemu-sta...@nongnu.org; Petar Jovanovic
Subject: Re: [Qemu-devel] Patch Round-up for stable 1.7.1, freeze on 2013-02-27
On 02/21/14 09:16, Michael Roth wrote:
> Hi everyone,
>
> The following new patches are queued for QEMU stable v1.7.1:
>
> htt
From: Petar Jovanovic
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions
From: Petar Jovanovic
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |5 +
target-mips/translate.c | 16
From: Petar Jovanovic
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR
Version 2 of the patch series to add mips32r5-generic model with UFR feature.
It includes extra patch to add support for Config4.
Petar Jovanovic (4):
target-mips: add CPU definition for MIPS32R5
target-mips: add support for CP0_Config4
target-mips: add support for CP0_Config5
target
From: Petar Jovanovic
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR
From: Petar Jovanovic
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions
From: Petar Jovanovic
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic
---
target-mips/cpu.h|3 +++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 15 +--
target-mips
From: Petar Jovanovic
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 14
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday
ping
From: Stefan Hajnoczi [stefa...@gmail.com]
Sent: Wednesday, January 08, 2014 5:52 AM
To: Petar Jovanovic
Cc: qemu-stable [qemu-sta...@nongnu.org]; qemu-devel@nongnu.org; Michael Roth
Subject: Re: [Qemu-devel] backport three changes for v1.7.1
On Wed
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
From: Petar Jovanovic
Sent: Tuesday, February 04, 2014 2:59 PM
To: Petar Jovanovic
014 2:51 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for
MIPS32R5
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
> From: Petar Jovanovic
>
> Add mips32r5-generic among CPU
From: Petar Jovanovic
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic
Reviewed-by: Eric Johnson
---
target-mips/cpu.h|3 +++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 15
p
for you to fetch changes up to 736d120af4bf5f3e13b2f90c464b3a24847f78f0:
target-mips: add user-mode FR switch support for MIPS32r5 (2014-02-10
16:46:38 +0100)
--------
Petar Jovanovic (4):
target-mips: add CPU definition fo
From: Petar Jovanovic
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR
From: Petar Jovanovic
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic
Reviewed-by: Eric Johnson
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips
From: Petar Jovanovic
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic
Reviewed-by: Eric Johnson
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files
From: Petar Jovanovic
FR bit should be initialized to 1 for MIPS64, under condition that this
bit is writable and that CPU has an FPU unit. It should be initialized to
zero for MIPS32.
This fixes different MIPS32 issues with FPU instructions whose behaviour
defaulted to 64-bit FPU mode.
Signed
ping
http://patchwork.ozlabs.org/patch/295442/
From: Andreas Färber [afaer...@suse.de]
Sent: Friday, November 29, 2013 6:04 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net; qemu-stable
Subject: Re: [Qemu-devel
From: Alex Bennée [alex.ben...@linaro.org]
Sent: Monday, November 04, 2013 5:46 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; riku.voi...@linaro.org;
Petar Jovanovic; aurel...@aurel32.net; afaer...@suse.de
Subject: Re: [Qemu
Can you please provide full reproduction steps rather than just an
assembly snippet?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1248168
Title:
MIPS, self-modifying code and uncached memory
Stat
From: Alex Bennée [alex.ben...@linaro.org]
Sent: Tuesday, November 05, 2013 3:46 PM
To: Petar Jovanovic
Cc: Petar Jovanovic; qemu-devel@nongnu.org; peter.mayd...@linaro.org;
riku.voi...@linaro.org; aurel...@aurel32.net; afaer...@suse.de
Subject: Re: [Qemu
ping
http://patchwork.ozlabs.org/patch/287211/
http://patchwork.ozlabs.org/patch/287213/
Riku?
Regards,
Petar
ping
http://patchwork.ozlabs.org/patch/287211/
http://patchwork.ozlabs.org/patch/287213/
From: Petar Jovanovic
Sent: Tuesday, November 12, 2013 4:40 PM
To: qemu-devel@nongnu.org; riku.voi...@linaro.org
Cc: Petar Jovanovic; peter.mayd...@linaro.org; aurel
ping
http://patchwork.ozlabs.org/patch/287211/
http://patchwork.ozlabs.org/patch/287213/
Can we get these two changes in 1.7?
It has been reviewed and waiting for someone who has commits rights for two
months now.
Regards,
Petar
From: Petar Jovanovic
ping
http://patchwork.ozlabs.org/patch/337703/
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Tuesday, April 08, 2014 7:24 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; riku.voi...@linaro.org
Subject: [PATCH] linux-user: fix getrusage and
From: Andreas Färber [afaer...@suse.de]
Sent: Monday, May 05, 2014 11:55 AM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: riku.voi...@linaro.org; Petar Jovanovic
Subject: Re: [Qemu-devel] [PATCH] linux-user: fix getrusage and wait4 failures
with invalid
From: Petar Jovanovic
Structs ipc_perm and shmid_ds are specific for each architecture and should
be defined accordingly. This change does that, and it also fix shmctl issue
by passing correct parameter buf to do_shmctl().
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c | 78
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Monday, October 07, 2013 6:08 PM
To: Petar Jovanovic
Cc: QEMU Developers; Riku Voipio; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH] linux-user: define ipc_perm and shmid_ds per
arch
This is a known issue.
There was a fix proposal by Thomas Schwinge back in June
http://patchwork.ozlabs.org/patch/250161/
but he has not updated the patch per suggestion ever since, though the patch
as is was much closer to correct behaviour than what it is now in the source.
If anyone is in hur
From: Petar Jovanovic
Creating target_structs header in linux-user/$arch/ and making
target_ipc_perm and target_shmid_ds its first inhabitants.
The struct defintions may/should be further fine-tuned by arch maintainers.
Signed-off-by: Petar Jovanovic
---
As suggested, this header can be used
From: Petar Jovanovic
Fix shmctl issue by passing correct parameter buf to do_shmctl().
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 4a14a43..1f6492e 100644
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Friday, October 11, 2013 9:10 PM
To: Petar Jovanovic
Cc: QEMU Developers; QEMU Trivial; Riku Voipio; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH] linux-user: pass correct parameter
Ping
http://patchwork.ozlabs.org/patch/281527/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Tuesday, October 08, 2013 7:32 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net; riku.voi...@linaro.org;
peter.mayd
From: Michael Tokarev [m...@tls.msk.ru]
Sent: Monday, October 21, 2013 10:45 AM
To: Petar Jovanovic
Cc: Peter Maydell; Petar Jovanovic; QEMU Trivial; Riku Voipio; QEMU Developers
Subject: Re: [Qemu-trivial] [Qemu-devel] [PATCH] linux-user: pass correct
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Monday, October 21, 2013 3:26 PM
To: Petar Jovanovic
Cc: Michael Tokarev; Petar Jovanovic; QEMU Trivial; Riku Voipio; QEMU Developers
Subject: Re: [Qemu-trivial] [Qemu-devel] [PATCH] linux-user: pass
Ping
http://patchwork.ozlabs.org/patch/281527/
From: Petar Jovanovic
Sent: Tuesday, October 15, 2013 2:44 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; riku.voi...@linaro.org; peter.mayd...@linaro.org
Subject: RE: [PATCH] linux
Ping
http://patchwork.ozlabs.org/patch/281527/
From: Petar Jovanovic
Sent: Tuesday, October 22, 2013 5:13 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; riku.voi...@linaro.org; peter.mayd...@linaro.org
Subject: RE: [PATCH] linux
From: Petar Jovanovic
Creating target_structs header in linux-user/$arch/ and making
target_ipc_perm and target_shmid_ds its first inhabitants.
The struct defintions may/should be further fine-tuned by arch maintainers.
Signed-off-by: Petar Jovanovic
---
v3:
- add GNU licence to the new header
From: Petar Jovanovic
Fix shmctl issue by passing correct parameter buf to do_shmctl().
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 4f9c558..abaffde 100644
1 - 100 of 156 matches
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