[Qemu-devel] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size

From: Bin Meng Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_e_prci.c | 2

[Qemu-devel] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree

From: Bin Meng This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 2 -- hw/riscv/

[Qemu-devel] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine

the file header says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/riscv_hart.c

[Qemu-devel] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

From: Bin Meng For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and SIFIVE_E_PRCI_HFXOSCCFG_EN should be used. Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv

[Qemu-devel] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 92 +++-- include/hw/riscv/sifive_u.h | 6 ++- 2 files changed

[Qemu-devel] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2

From: Bin Meng It is not useful if we only have one management CPU. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis [Palmer: Set default CPUs to 2] Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 5 - include/hw/riscv/sifive_u.h | 2

[Qemu-devel] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead

From: Bin Meng Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...) in various sifive models. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c | 8 +--- hw/riscv/sifive_test.c | 5 +++-- hw/riscv

[Qemu-devel] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

ions. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/Makefile.objs | 2 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 79 ++--

[Qemu-devel] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540

From: Bin Meng This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/Makefile.objs | 1 + hw/riscv

[Qemu-devel] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h

From: Bin Meng The inclusion of "target/riscv/cpu.h" is unnecessary in various sifive model drivers. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c | 1 - hw/riscv/sifive_test.c | 1 - hw/riscv/sifive_uart.c | 1

[Qemu-devel] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes

From: Bin Meng To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 23

[Qemu-devel] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string

From: Bin Meng With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: Fabien Chouteau Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 7

[Qemu-devel] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP

Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_otp.c | 191 include/hw/riscv/sifive_u_otp.h | 80 + 3 files changed, 272 insertions(+) create mode 100644 hw/riscv/sifive_u_otp.c create mode

[Qemu-devel] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines

From: Bin Meng Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_cpu.h | 31 +++ include/hw/riscv

[Qemu-devel] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC

From: Bin Meng Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 24 +++- include/hw

[Qemu-devel] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number

From: Bin Meng This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv

[Qemu-devel] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array

ed based on the property value. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/riscv_hart.c | 3 ++- include/hw/riscv/riscv_hart.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/ris

[Qemu-devel] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet

hem any more. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 24 +--- include/hw/riscv/sifive_u.h | 3 +-- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/riscv/sifive_u.c b/

[Qemu-devel] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs

From: Bin Meng This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 4 ++-- include/hw/riscv/sifive_u.h

[Qemu-devel] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine

From: Bin Meng With the support of heterogeneous harts and PRCI model, it's now possible to use the OpenSBI image (PLATFORM=sifive/fu540) built for the real hardware. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- pc-bios/opensbi-riscv64-sif

[Qemu-devel] [PULL 45/48] target/riscv: Use both register name and ABI name

From: Atish Patra Use both the generic register name and ABI name for the general purpose registers and floating point registers. Signed-off-by: Atish Patra Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 19

[Qemu-devel] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes

From: Bin Meng Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c

[Qemu-devel] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree

e name as "/soc/uart@...", causing U-Boot fail to find the serial node in DT. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.

[Qemu-devel] [PULL 42/48] riscv: sifive_u: Fix broken GEM support

reg base & size to the property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/Kconfig| 1 + hw/riscv/sifive_u.c | 24 includ

[Qemu-devel] [PULL 46/48] target/riscv: Fix mstatus dirty mask

From: Alistair Francis This is meant to mask off the hypervisor bits, but a typo caused it to mask MPP instead. Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits") Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- ta

[Qemu-devel] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree

From: Bin Meng This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 5 +++-- 1 file changed, 3

[Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point

From: Alistair Francis Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb flags. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target

[Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers

umber (8). It should use the csr_register_map in order to reach the riscv_cpu_get_fflags callback. Signed-off-by: KONRAD Frederic Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/targ

[Qemu-devel] [PULL 10/48] riscv: Add a helper routine for finding firmware

From: Bin Meng This adds a helper routine for finding firmware. It is currently used only for "-bios default" case. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 22 +++--- include/hw/riscv/boot.h

Re: [PATCH v1 16/28] target/riscv: Add hypvervisor trap support

ECALL)) | -(1ULL << (RISCV_EXCP_S_ECALL)) | - (1ULL << (RISCV_EXCP_H_ECALL)) | +(1ULL << (RISCV_EXCP_VS_ECALL)) | +(1ULL << (RISCV_EXCP_HS_ECALL)) | (1ULL << (RISCV_EXCP_M_ECALL)) | (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 0/6] RISC-V: Add more machine memory

On Thu, 19 Sep 2019 15:24:51 PDT (-0700), Alistair Francis wrote: This series aims to improve the use of QEMU for developing boot code. It does a few things: - sifive_u machine: - Adds a chunk of memory in the Flash area. This allows boot loaders to use this memory. I can't find details o

Re: [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access

On Tue, 17 Sep 2019 09:37:47 PDT (-0700), alistai...@gmail.com wrote: On Tue, Sep 17, 2019 at 6:56 AM Peter Maydell wrote: On Fri, 16 Aug 2019 at 09:57, Peter Maydell wrote: > > On Thu, 15 Aug 2019 at 23:17, Palmer Dabbelt wrote: > > You're more than welcome to take the

Re: [PATCH v1 0/2] RISC-V: Convert to do_transaction_failed hook

4:target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); translate.c:782:ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); gdbstub.c:328:env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ All of these look safe to me. Palmer Dabbelt (2): RISC-V: Handle bu

Re: [PATCH v8 0/3] RTC support for QEMU RISC-V virt machine

On Wed, 06 Nov 2019 03:56:29 PST (-0800), Anup Patel wrote: This series adds RTC device to QEMU RISC-V virt machine. We have selected Goldfish RTC device model for this. It's a pretty simple synthetic device with few MMIO registers and no dependency external clock. The driver for Goldfish RTC is

Re: [PATCH for 4.2 v1 1/1] riscv/virt: Increase flash size

[VIRT_DRAM] ={ 0x8000, 0x0 }, [VIRT_PCIE_MMIO] = { 0x4000,0x4000 }, [VIRT_PCIE_PIO] ={ 0x0300,0x0001 }, Reviewed-by: Palmer Dabbelt I'll include this in my next PR, which should be soon -- I was about to send it, but figure I should look at my email first :)

[PATCH] RISC-V: virt: This is a "sifive,test1" test finisher

a2551ed6f ("riscv: sifive_test: Add reset functionality") Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 23f340df19..74f2dce81c 100644 ---

Re: [PATCH] RISC-V: virt: This is a "sifive,test1" test finisher

On Fri, 08 Nov 2019 10:04:47 PST (-0800), Peter Maydell wrote: On Fri, 8 Nov 2019 at 17:15, Alistair Francis wrote: On Fri, Nov 8, 2019 at 9:05 AM Palmer Dabbelt wrote: > > The test finisher implements the reset command, which means it's a > "sifive,test1" devi

[PATCH v2 2/3] ARM/virt: Use fdt_setprop_strings()

ned-off-by: Palmer Dabbelt --- hw/arm/virt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc2607..4dc00f54d5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -304,9 +304,8 @@ static void fdt_add_timer_nodes(const VirtMachine

[PATCH v2 1/3] device_tree: Add a helper function for string arrays

the array ["string1", "string2"] is represeted as "string1\0string2\0". The DTB generated by this function is accepted by DTC and produces an array of strings, but I can't find any explicit line in the DT specification that defines how these are encoded. Sign

[PATCH v2 0/3] device_tree: Allow for and use string arrays [Was: RISC-V: virt: This is a "sifive, test1" test finisher]

Device trees commonly contain arrays of strings for compatible nodes. We recently extended the "sifive,test0" node in a backwards-compatible way, but QEMU didn't contain an FDT function to set 'compatible = "sifive,test1", "sifive,test0";'. I've converted over the code from the ARM virt board that

[PATCH v2 3/3] RISC-V: virt: This is a "sifive,test1" test finisher

The test finisher implements the reset command, which means it's a "sifive,test1" device. This is a backwards compatible change, so it's also a "sifive,test0" device. Fixes: 9a2551ed6f ("riscv: sifive_test: Add reset functionality") Signed-off-by: Palmer

[PULL] RISC-V Fixes for 4.2-rc2

The following changes since commit aa464db69b40b4b695be31085e6d2f1e90956c89: Update version for v4.2.0-rc1 release (2019-11-12 18:40:02 +) are available in the Git repository at: g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-rc2 for you to fetch changes up to 6911fde

[PULL 1/4] remove unnecessary ifdef TARGET_RISCV64

From: "hiroyuki.obinata" Signed-off-by: Hiroyuki Obinata Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b26533d4fd78..ab6a891dc381 100644 --

[PULL 3/4] opensbi: Upgrade from v0.4 to v0.5

: do not use relocated _boot_status before it is valid Nylon Chen (3): firmware: Fix the loop condition of _wait_relocate_copy_done section platform: Add Andes AE350 initial support scripts: Add AE350 to platform list in the binary archive script Palmer Dabbelt (1): Include `git

[PULL 2/4] target/riscv: Remove atomic accesses to MIP CSR

chard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c| 5 ++-- target/riscv/cpu.h| 9 target/riscv/cpu_helper.c | 48 +++ target/riscv/csr.c| 2 +- 4

[PULL 4/4] riscv/virt: Increase flash size

at is 32MB. No QEMU release has include flash in the RISC-V virt machine, so this isn't a breaking change. Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/vi

Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonat...@fintelia.io wrote: Ping! What is the status of this patch? Sorry, I must have lost track of it. I've added it to my patch queue. On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens wrote: Bin, that proposal proved to be somewhat more controv

Re: [Qemu-devel] RISC-V: Vector && DSP Extension

On Thu, 15 Aug 2019 14:37:52 PDT (-0700), alistai...@gmail.com wrote: On Thu, Aug 15, 2019 at 2:07 AM Peter Maydell wrote: On Thu, 15 Aug 2019 at 09:53, Aleksandar Markovic wrote: > > > We can accept draft > > extensions in QEMU as long as they are disabled by default. > Hi, Alistair, Palmer

Re: [Qemu-devel] [PATCH 0/2] riscv: Fix "-L" not working for bios image search path

On Fri, 16 Aug 2019 06:09:34 PDT (-0700), bmeng...@gmail.com wrote: Currently when QEMU is given a bios image with only a file name and its file path passed in "-L", it still reports file not found. This series fixes the issue. This is especially helpful for creating distro QEMU packages. Bin

Re: [Qemu-devel] [PATCH v4] riscv: hmp: Add a command to show virtual memory mappings

by merging all contiguous physical address mappings into one block and only shows the merged block mapping details. Signed-off-by: Bin Meng Acked-by: Dr. David Alan Gilbert Reviewed-by: Palmer Dabbelt --- Changes in v4: - restore to v2, that does not print all harts's PTE, since we sho

Re: [Qemu-devel] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit

On Sun, 18 Aug 2019 23:00:40 PDT (-0700), bmeng...@gmail.com wrote: On Wed, Aug 14, 2019 at 5:46 PM Bin Meng wrote: Hi Palmer, On Sat, Aug 10, 2019 at 9:49 AM Alistair Francis wrote: > > On Wed, Aug 7, 2019 at 7:50 PM Bin Meng wrote: > > > > For RV32, the root page table's PPN has 22 bits h

Re: [Qemu-devel] RISC-V: Vector && DSP Extension

On Thu, 22 Aug 2019 15:37:15 PDT (-0700), alistai...@gmail.com wrote: On Wed, Aug 21, 2019 at 6:56 PM liuzhiwei wrote: On 2019/8/22 上午3:31, Palmer Dabbelt wrote: > On Thu, 15 Aug 2019 14:37:52 PDT (-0700), alistai...@gmail.com wrote: >> On Thu, Aug 15, 2019 at 2:07 AM Peter Maydell

[PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes

From: Bin Meng The "clock-frequency" property of cpu nodes isn't required. Drop it. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133031/ Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt

[PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node

Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 02dd76176e..1ac51e3632 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -270,6 +270,10 @@ static

[PULL 09/18] riscv/sifive_u: Manually define the machine

From: Alistair Francis Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: P

[PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs

: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e8d8..cb5bfd3d50 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7

[PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode

Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f767ad24be..974c9c20b5 100644 --- a/target/riscv/csr.c +++ b/target/r

[PULL 16/18] target/riscv: Make the priv register writable by GDB

M-mode. Signed-off-by: Jonathan Behrens Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index

[PULL 02/18] RISC-V: Handle bus errors in the page table walker

Dabbelt Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv

[PULL 03/18] RISC-V: Implement cpu_do_transaction_failed

This converts our port over from cpu_do_unassigned_access to cpu_do_transaction_failed, as cpu_do_unassigned_access has been deprecated. Signed-off-by: Palmer Dabbelt Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer

[PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory

g it be re returned to all enabled from a reset. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 16 include/hw/riscv/sifive_u.h | 1 + 2 files changed, 17 insertions(+) diff --git a/hw/riscv/sifive_u.c

[PULL 08/18] riscv/sifive_u: Add QSPI memory region

using QEMU's -device loader command line option. In the future we can look at adding a model for the is25wp256 flash. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 8 include/hw/riscv/sifive_u.h | 1 + 2 files

[PULL 13/18] riscv/virt: Jump to pflash if specified

From: Alistair Francis If the user supplied pflash to QEMU then change the reset code to jump to the pflash base address instead of the DRAM base address. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Tested-by: Bin Meng Signed-off-by: Palmer

[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2

h 'remotes/mst/tags/for_upstream' into staging (2019-10-28 13:32:40 +) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf2 for you to fetch changes up to 9667e53573f907d4fcd6accff1c8fe525544b749: target/riscv: PMP violati

[PULL 10/18] riscv/sifive_u: Add the start-in-flash property

From: Alistair Francis Add a property that when set to true QEMU will jump from the ROM code to the start of flash memory instead of DRAM which is the default behaviour. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv

[PULL 06/18] linux-user/riscv: Propagate fault address

environment structure. In case of memory faults store the exception address into `siginfo`. Signed-off-by: Giuseppe Musacchio Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- linux-user/riscv/cpu_loop.c | 3 ++- target/riscv/cpu_helper.c | 5 - 2 files changed, 6 insertions(+), 2

[PULL 11/18] riscv/virt: Manually define the machine

ff-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 30 -- include/hw/riscv/virt.h | 7 ++- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c

[PULL 15/18] target/riscv: Expose "priv" register for GDB for reads

Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- configure | 4 ++-- gdb-xml/riscv-32bit-virtual.xml | 11 +++ gdb-xml/riscv-64bit-virtual.xml | 11 +++ target/riscv/gdbstub.c | 23 +++ 4 files c

[PULL 12/18] riscv/virt: Add the PFlash CFI01 device

Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/Kconfig| 1 + hw/riscv/virt.c | 86 + include/hw/riscv/virt.h | 3 ++ 3 files changed, 90 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fb19b2df3a

[PULL 18/18] target/riscv: PMP violation due to wrong size parameter

starting address of the range, as `addr - 1` is not in the range. In order to fix, we just assume that all bytes from addr to the end of the page will be accessed if the size is unknown. Signed-off-by: Dayeol Lee Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c

[PULL 17/18] riscv/boot: Fix possible memory leak

eviewed-by: Richard Henderson Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2e92fb0680..7fee98d2f8 100644 ---

Re: [PATCH v1 1/1] opensbi: Upgrade from v0.4 to v0.5

On Sat, 26 Oct 2019 01:46:45 PDT (-0700), phi...@redhat.com wrote: On Sat, Oct 26, 2019 at 10:45 AM Philippe Mathieu-Daudé wrote: Hi Alistair, On 10/26/19 1:15 AM, Alistair Francis wrote: > This release has: > Lot of critical fixes > Hypervisor extension support > SBI v0.2 base

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

On Tue, 29 Oct 2019 03:49:23 PDT (-0700), alistai...@gmail.com wrote: On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis wrote: On Fri, Oct 18, 2019 at 9:51 AM Palmer Dabbelt wrote: > > On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote: > > Instead of relying o

[Bug 1850378] Re: RISC-V unreliable IPIs

Can you post a whole program that reproduces this? freedom-e-sdk will run bare-metal code on QEMU if you don't want to post the rest of the surrounding infrastructure. -- You received this bug notification because you are a member of qemu- devel-ml, whic

[PATCH] MAINTAINERS: Change to my personal email address

I'm leaving SiFive in a bit less than two weeks, which means I'll be losing my @sifive email address. I don't have my new email address yet, so I'm switching over to my personal address instead. Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- MAINTAIN

[PULL] MAINTAINERS: Change to my personal email address

I'm leaving SiFive in a bit less than two weeks, which means I'll be losing my @sifive email address. I don't have my new email address yet, so I'm switching over to my personal address. Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbe

[PULL] Update my MAINTAINERS file entry

The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b: Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/palmer-

Re: [PATCH] remove unnecessary ifdef TARGET_RISCV64

64 -[3] = MO_TEQ, [6] = MO_TEUL, -#endif }; #endif Reviewed-by: Palmer Dabbelt This is a non-functional change (the code in question was already wrapped in an "#ifdef TARGET_RISCV64", so this internal one was redundant), so I'm happy to include it during the soft freeze.

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

On Tue, 29 Oct 2019 23:54:30 PDT (-0700), alistai...@gmail.com wrote: On Tue, Oct 29, 2019 at 4:14 PM Palmer Dabbelt wrote: On Tue, 29 Oct 2019 03:49:23 PDT (-0700), alistai...@gmail.com wrote: > On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis wrote: >> >> On Fri, Oct 18,

Re: [PATCH v5 0/2] RTC support for QEMU RISC-V virt machine

On Fri, 01 Nov 2019 08:40:24 PDT (-0700), a...@brainfault.org wrote: On Tue, Oct 29, 2019 at 6:55 PM Alistair Francis wrote: On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote: > > This series adds RTC device to QEMU RISC-V virt machine. We have > selected Goldfish RTC device model for this. It

Re: [PATCH v5 0/2] RTC support for QEMU RISC-V virt machine

On Sat, 02 Nov 2019 03:37:42 PDT (-0700), Peter Maydell wrote: On Tue, 29 Oct 2019 at 13:25, Alistair Francis wrote: On Fri, Oct 25, 2019 at 6:28 AM Anup Patel wrote: > > This series adds RTC device to QEMU RISC-V virt machine. We have > selected Goldfish RTC device model for this. It's a pre

Re: [PATCH v1 1/1] opensbi: Upgrade from v0.4 to v0.5

On Tue, 05 Nov 2019 11:23:39 PST (-0800), alistai...@gmail.com wrote: > On Tue, Oct 29, 2019 at 3:33 AM Alistair Francis wrote: >> >> On Mon, Oct 28, 2019 at 5:56 PM Palmer Dabbelt wrote: >> > >> > On Sat, 26 Oct 2019 01:46:45 PDT (-0700), phi...@redhat.com wrot

Re: Adding New, Unsupported ISA to Qemu

On Tue, 05 Nov 2019 08:42:53 PST (-0800), stefa...@gmail.com wrote: On Mon, Nov 04, 2019 at 11:50:11PM +, Hanson, Seth via wrote: I'm looking for in-depth documentation pertaining to how an unsupported 16 bit RISC ISA can be emulated in Qemu. I've referenced this: https://wiki.qemu.org/Do

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

On Mon, 23 Mar 2020 19:08:19 PDT (-0700), bmeng...@gmail.com wrote: Hi Palmer, On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis wrote: At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generat

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

On Tue, 21 Apr 2020 10:40:05 PDT (-0700), alistai...@gmail.com wrote: On Mon, Apr 20, 2020 at 7:17 PM Bin Meng wrote: On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis wrote: > > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng wrote: > > > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng wrote: > > > >

[PULL 6/6] riscv/sifive_u: Add a serial property to the sifive_u machine

reated and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt R

[PULL 1/6] target/riscv: Don't set write permissions on dirty PTEs

guest (VU) becoming corrupted. This appears to be because it ends up with write permission in the second stage translation in cases where we aren't doing a store. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 6 ++ 1 fi

[PULL 2/6] riscv: Don't use stage-2 PTE lookup protection flags

From: Alistair Francis When doing the fist of a two stage lookup (Hypervisor extensions) don't set the current protection flags from the second stage lookup of the base address PTE. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/

[PULL] RISC-V Patches for 5.0-rc4

The following changes since commit 20038cd7a8412feeb49c01f6ede89e36c8995472: Update version for v5.0.0-rc3 release (2020-04-15 20:51:54 +0100) are available in the Git repository at: g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-rc4 for you to fetch changes up to 8a7ce6a

[PULL 3/6] riscv: AND stage-1 and stage-2 protection flags

From: Alistair Francis Take the result of stage-1 and stage-2 page table walks and AND the two protection flags together. This way we require both to set permissions instead of just stage-2. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt

[PULL 5/6] riscv/sifive_u: Add a serial property to the sifive_u SoC

ned-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 8 +++- include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d0

[PULL 4/6] riscv/sifive_u: Fix up file ordering

From: Alistair Francis Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 109 ++-- 1 file changed, 55 insertions(+), 54 deletions(-) diff

Re: [PULL] RISC-V Patches for 5.0-rc4

On Tue, 21 Apr 2020 12:27:50 PDT (-0700), Peter Maydell wrote: On Tue, 21 Apr 2020 at 20:19, Palmer Dabbelt wrote: RISC-V Patches for 5.0-rc4 This contains handful of patches that I'd like to target for 5.0. I know it&#x

[PULL 1/6] target/riscv: Correctly implement TSR trap

From: Alistair Francis As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set a

[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5

The following changes since commit a98135f727595382e200d04c2996e868b7925a01: Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 14:55:59 +) are available in the Git repository at: g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-m

[PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit

From: Bin Meng Update BIOS_FILENAME to consider 32-bit bios image file name. Tested booting Linux v5.5 32-bit image (built from rv32_defconfig plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt

[PULL 6/6] target/riscv: Fix VS mode interrupts forwarding.

interrupt, the VS mode forwarding check does not work as intended and interrupt is actually forwarded to hypervisor. This patch fixes this issue. Signed-off-by: Rajnesh Kanwal Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 9 - 1 file changed, 8

[PULL 3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine

for sifive_u machine. A pre-built OpenSBI v0.6 image has been added as the default bios for 32-bit sifive_u machine. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- Makefile | 2 +- pc-bios/opensbi-riscv32-sifive_u

[PULL 2/6] roms: opensbi: Upgrade from v0.5 to v0.6

b3bb8 lib: Simplify the for-loop in sbi_ipi_send_many() ac5e821 include: Bump-up version to 0.6 Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 40984 -> 41280 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.b

[PULL 5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries

ned-off-by: Bin Meng Signed-off-by: Palmer Dabbelt --- .gitlab-ci-opensbi.yml | 63 + .gitlab-ci.d/opensbi/Dockerfile | 33 + .gitlab-ci.yml | 1 + 3 files changed, 97 insertions(+) create mode 100644 .gitlab-ci-opensbi.yml

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