merged tag 'for_upstream'
Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
The following changes since commit 9bb73502321d46f4d320fa17aa38201445783fc4:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2019-10-28 13:32:40 +0000)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf2
for you to fetch changes up to 9667e53573f907d4fcd6accff1c8fe525544b749:
target/riscv: PMP violation due to wrong size parameter (2019-10-28 08:46:33
-0700)
----------------------------------------------------------------
RISC-V Patches for the 4.2 Soft Freeze, Part 2
This patch set contains a handful of small fixes for RISC-V targets that
I'd like to target for the 4.2 soft freeze. They include:
* A fix to allow the debugger to access the state of all privilege
modes, as opposed to just the currently executing one.
* A pair of cleanups to implement cpu_do_transaction_failed.
* Fixes to the device tree.
* The addition of various memory regions to make the sifive_u machine
more closely match the HiFive Unleashed board.
* Fixes to our GDB interface to allow CSRs to be accessed.
* A fix to a memory leak pointed out by coverity.
* A fix that prevents PMP checks from firing incorrectly.
This passes "make chcek" and boots Open Embedded for me.
----------------------------------------------------------------
Alistair Francis (8):
riscv/sifive_u: Add L2-LIM cache memory
riscv/sifive_u: Add QSPI memory region
riscv/sifive_u: Manually define the machine
riscv/sifive_u: Add the start-in-flash property
riscv/virt: Manually define the machine
riscv/virt: Add the PFlash CFI01 device
riscv/virt: Jump to pflash if specified
riscv/boot: Fix possible memory leak
Bin Meng (3):
riscv: Skip checking CSR privilege level in debugger mode
riscv: hw: Drop "clock-frequency" property of cpu nodes
riscv: sifive_u: Add ethernet0 to the aliases node
Dayeol Lee (1):
target/riscv: PMP violation due to wrong size parameter
Giuseppe Musacchio (1):
linux-user/riscv: Propagate fault address
Jonathan Behrens (3):
target/riscv: Tell gdbstub the correct number of CSRs
target/riscv: Expose "priv" register for GDB for reads
target/riscv: Make the priv register writable by GDB
Palmer Dabbelt (2):
RISC-V: Handle bus errors in the page table walker
RISC-V: Implement cpu_do_transaction_failed
configure | 4 +-
gdb-xml/riscv-32bit-virtual.xml | 11 ++++
gdb-xml/riscv-64bit-virtual.xml | 11 ++++
hw/riscv/Kconfig | 1 +
hw/riscv/boot.c | 11 ++--
hw/riscv/sifive_u.c | 105 ++++++++++++++++++++++++++------
hw/riscv/spike.c | 2 -
hw/riscv/virt.c | 129 +++++++++++++++++++++++++++++++++++++---
include/hw/riscv/sifive_u.h | 12 +++-
include/hw/riscv/spike.h | 4 --
include/hw/riscv/virt.h | 14 +++--
linux-user/riscv/cpu_loop.c | 3 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 7 ++-
target/riscv/cpu_helper.c | 28 ++++++---
target/riscv/csr.c | 5 +-
target/riscv/gdbstub.c | 36 ++++++++++-
target/riscv/pmp.c | 13 +++-
18 files changed, 334 insertions(+), 64 deletions(-)
create mode 100644 gdb-xml/riscv-32bit-virtual.xml
create mode 100644 gdb-xml/riscv-64bit-virtual.xml
