On Tue, 05 Nov 2019 08:42:53 PST (-0800), stefa...@gmail.com wrote:
On Mon, Nov 04, 2019 at 11:50:11PM +0000, Hanson, Seth via wrote:
I'm looking for in-depth documentation pertaining to how an unsupported 16 bit
RISC ISA can be emulated in Qemu.
I've referenced this:
https://wiki.qemu.org/Documentation/TCG
and have been hoping there's additional, related documentation that I've
overlooked.
The general advice I've seen is:
1. Look at existing TCG targets to learn how to implement aspects of
your ISA.
Michael wrote a pair of blogs describing our port. They're part of the "All
Aboard" series, which details the RISC-V ports of the various core software
components (binutils, GCC, glibc, Linux, and QEMU):
https://www.sifive.com/blog/risc-v-qemu-part-1-privileged-isa-hifive1-virtio
https://www.sifive.com/blog/risc-v-qemu-part-2-the-risc-v-qemu-port-is-upstream
It's a whole different thing than the documentation and is two years out of
date, but it at least provides some perspective on why certain things in our
port were done the way they were in caesy ou end up looking at the code.>
2. If you are unfamiliar with emulation, CPU ISA, or just-in-time
compiler concepts, try to read up on them and then look back at the
QEMU code. Things will be clearer.
You're welcome to join #qemu IRC on irc.oftc.net to ask questions.
Good luck!
Stefan
