Set the state of each ISA extension on the vcpu depending on what
is set in the CPU property and what is allowed by KVM for that extension.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 11 -
target/riscv/kvm.c
https://github.com/mdchitale/qemu.git
Changes in v2:
- Rebase to latest riscv-to-apply.next
- Update linux headers to version 6.1-rc8
- Add reviewed by tags
Mayuresh Chitale (3):
update-linux-headers: Version 6.1-rc8
target/riscv: Extend isa_ext_data for single letter extensions
target/riscv
extensions from the list of single letter extensions as those are not
supported yet.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 41 +++--
1 file changed, 23 insertions(+), 18 deletions(-)
Sync headers with kernel commit 76dcd734eca2
Signed-off-by: Mayuresh Chitale
Reviewed-by: Andrew Jones
---
include/standard-headers/drm/drm_fourcc.h | 34 -
include/standard-headers/linux/ethtool.h | 63 +++-
include/standard-headers/linux/fuse.h | 6 +-
.../linux
On Fri, 2022-07-22 at 08:31 +0800, Weiwei Li wrote:
> 在 2022/7/21 下午11:31, Mayuresh Chitale 写道:
> > Smstateen extension specifies a mechanism to close
> > the potential covert channels that could cause security issues.
> >
> > This patch adds the CSRs defined in th
On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote:
> 在 2022/7/21 下午11:31, Mayuresh Chitale 写道:
> > If smstateen is implemented and sstateen0.fcsr is clear then the
> > floating point operations must return illegal instruction
> > exception.
> >
> >
On Mon, 2022-07-25 at 15:11 +0800, Weiwei Li wrote:
> 在 2022/7/24 下午11:39, Mayuresh Chitale 写道:
> > On Fri, 2022-07-22 at 08:31 +0800, Weiwei Li wrote:
> > > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道:
> > > > Smstateen extension specifies a mechanism to close
> &g
On Mon, 2022-07-25 at 15:23 +0800, Weiwei Li wrote:
>
> 在 2022/7/24 下午11:49, Mayuresh Chitale 写道:
> > On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote:
> > > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道:
> > > > If smstateen is implemented and sstatee
On Fri, 2022-07-22 at 08:45 +0800, Weiwei Li wrote:
> 在 2022/7/21 下午11:31, Mayuresh Chitale 写道:
> > Accesses to henvcfg, henvcfgh and senvcfg are allowed only if
> > corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an
> > illegal instruction trap is generated.
&
On Thu, 2022-07-28 at 09:09 +0100, Ben Dooks wrote:
> On 28/07/2022 07:15, Mayuresh Chitale wrote:
> > On Mon, 2022-07-25 at 15:23 +0800, Weiwei Li wrote:
> > > 在 2022/7/24 下午11:49, Mayuresh Chitale 写道:
> > > > On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote:
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if
corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an
illegal instruction trap is generated.
Signed-off-by: Mayuresh Chitale
---
roms/opensbi | 2 +-
target/riscv/csr.c | 83
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d4635c7df4..d8a0f4e700 100644
--- a/target
Changes in v2:
- Make h/s/envcfg bits in m/h/stateen registers as writeable by default.
Anup Patel (1):
target/riscv: Force disable extensions if priv spec version does not
match
Mayuresh Chitale (4):
target/riscv: Add smstateen support
target/riscv: smstateen check for h/senvcfg
target
If smstateen is implemented and sstateen0.fcsr is clear then the
floating point operations must return illegal instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c| 23 +
target/riscv/insn_trans/trans_rvf.c.inc | 40
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.h | 4
On Wed, 2022-08-03 at 16:15 +0800, Weiwei Li wrote:
> 在 2022/8/2 上午1:18, Mayuresh Chitale 写道:
> > Smstateen extension specifies a mechanism to close
> > the potential covert channels that could cause security issues.
> >
> > This patch adds the CSRs defined in th
On Wed, 2022-08-03 at 16:24 +0800, Weiwei Li wrote:
> 在 2022/8/2 上午1:18, Mayuresh Chitale 写道:
> > Accesses to henvcfg, henvcfgh and senvcfg are allowed only if
> > corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an
> > illegal instruction trap is generated.
&
On Wed, 2022-08-03 at 16:32 +0800, Weiwei Li wrote:
> 在 2022/8/2 上午1:18, Mayuresh Chitale 写道:
> > If smstateen is implemented and sstateen0.fcsr is clear then the
> > floating point operations must return illegal instruction
> > exception.
>
> I think this is not corre
rule #3 the comment.
Changes in v4:
- Fix build issue with riscv32/riscv64-linux-user targets
Changes in v3:
- Fix coding style issues
- Fix *stateen0h index calculation
Changes in v2:
- Make h/s/envcfg bits in m/h/stateen registers as writeable by default.
Mayuresh Chitale (4):
target/riscv
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.h | 4
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 87 ++
1 file changed
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d4635c7df4..d8a0f4e700 100644
--- a/target
If smstateen is implemented and sstateen0.fcsr is clear then the floating point
operations must return illegal instruction exception or virtual instruction
trap, if relevant.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c| 23 +
target/riscv
On Fri, Mar 24, 2023 at 7:01 PM liweiwei wrote:
>
>
> On 2022/11/21 07:35, Alistair Francis wrote:
> > On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale
> > wrote:
> >> If smstateen is implemented and sstateen0.fcsr is clear then the floating
> >> po
If misa.F and smstateen_fcsr_ok flag are clear then all the floating
point instructions must generate an appropriate exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/insn_trans/trans_rvf.c.inc | 24 ---
target/riscv/insn_trans/trans_rvzfh.c.inc | 4
2
If smstateen is implemented and sstateen0.fcsr is clear then the
floating point operations must return illegal instruction exception
or virtual instruction trap, if relevant.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.h | 3 +++
target/riscv/csr.c | 25 -
2
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
.
Mayuresh Chitale (4):
target/riscv: smstateen check for fcsr
target/riscv: Add fcsr field in tb->flags
target/riscv: check smstateen fcsr flag
target/riscv: smstateen knobs
target/riscv/cpu.c| 3 ++-
target/riscv/cpu.h| 4
target/ri
The state of smstateen0.FCSR bit impacts the execution of floating point
instructions when misa.F==0. Add a field in the tb->flags which stores
the current state of smstateen0.fcsr and will be used by floating point
translation routines.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cp
On Wed, May 17, 2023 at 8:42 AM Alistair Francis wrote:
>
> On Tue, May 2, 2023 at 12:00 AM Mayuresh Chitale
> wrote:
> >
> > If smstateen is implemented and smtateen0.fcsr is clear and misa.F
> > is off then the floating point operations must return illegal
> >
On Mon, Apr 10, 2023 at 8:00 PM liweiwei wrote:
>
>
> On 2023/4/10 22:13, Mayuresh Chitale wrote:
> > If misa.F and smstateen_fcsr_ok flag are clear then all the floating
> > point instructions must generate an appropriate exception.
> >
> > Signed-off-by: Mayur
On Mon, Apr 10, 2023 at 8:14 PM liweiwei wrote:
>
>
> On 2023/4/10 22:13, Mayuresh Chitale wrote:
> > If smstateen is implemented and sstateen0.fcsr is clear then the
> > floating point operations must return illegal instruction exception
> > or virtual instruction
On Tue, Apr 11, 2023 at 7:23 AM Richard Henderson
wrote:
>
> On 4/10/23 07:13, Mayuresh Chitale wrote:
> > +#ifndef CONFIG_USER_ONLY
> > +#define smstateen_fcsr_check(ctx) do { \
> > +if (!ctx->smstateen_fcsr_ok) { \
> > +if (ctx->virt_enabled) { \
On Tue, Apr 11, 2023 at 7:17 AM Richard Henderson
wrote:
>
> On 4/10/23 07:13, Mayuresh Chitale wrote:
> > The state of smstateen0.FCSR bit impacts the execution of floating point
> > instructions when misa.F==0. Add a field in the tb->flags which stores
> > the curre
If misa.F and smstateen_fcsr_ok flag are clear then all the floating
point instructions must generate an appropriate exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/insn_trans/trans_rvd.c.inc | 13
target/riscv/insn_trans/trans_rvf.c.inc | 24
If smstateen is implemented and smtateen0.fcsr is clear and misa.F
is off then the floating point operations must return illegal
instruction exception or virtual instruction trap, if relevant.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 23 +++
1 file changed
in v2:
- Improve patch 1 description
- Reuse TB_FLAGS.HS_FS for smstateen
- Convert smstateen_fcsr_check to function
- Add fcsr check for zdinx
Mayuresh Chitale (4):
target/riscv: smstateen check for fcsr
target/riscv: Reuse TB_FLAGS.MSTATUS_HFS_FS
target/riscv: check smstateen fcsr flag
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
When misa.F is clear, TB_FLAGS.MSTATUS_HS_FS field is unused and can
be used to save the current state of smstateen0.FCSR check which is
needed by the floating point translation routines.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu_helper.c | 12
target/riscv/translate.c
On Sat, Apr 15, 2023 at 6:32 AM Weiwei Li wrote:
>
>
> On 2023/4/15 00:01, Mayuresh Chitale wrote:
> > If smstateen is implemented and smtateen0.fcsr is clear and misa.F
> > is off then the floating point operations must return illegal
> > instruction exception or v
On Sat, Apr 15, 2023 at 7:15 AM Weiwei Li wrote:
>
>
> On 2023/4/15 00:02, Mayuresh Chitale wrote:
> > When misa.F is clear, TB_FLAGS.MSTATUS_HS_FS field is unused and can
> > be used to save the current state of smstateen0.FCSR check which is
> > needed by the floating
On Sat, Apr 15, 2023 at 6:55 AM Weiwei Li wrote:
>
>
> On 2023/4/15 00:02, Mayuresh Chitale wrote:
> > If misa.F and smstateen_fcsr_ok flag are clear then all the floating
> > point instructions must generate an appropriate exception.
> >
> > Signed-off-by: Mayur
If misa.F and smstateen_fcsr_ok flag are clear then all the floating
point instructions must generate an appropriate exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/insn_trans/trans_rvd.c.inc | 13 ++---
target/riscv/insn_trans/trans_rvf.c.inc | 24 ++---
target
Mayuresh Chitale (4):
target/riscv: smstateen check for fcsr
target/riscv: Reuse tb->flags.FS
target/riscv: check smstateen fcsr flag
target/riscv: smstateen knobs
target/riscv/cpu.c| 3 ++-
target/riscv/cpu_helper.c | 9 +++
target/riscv/cs
When misa.F is 0 tb->flags.FS field is unused and can be used to save
the current state of smstateen0.FCSR check which is needed by the
floating point translation routines.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu_helper.c | 9 +
target/riscv/translate.c |
If smstateen is implemented and smtateen0.fcsr is clear and misa.F
is off then the floating point operations must return illegal
instruction exception or virtual instruction trap, if relevant.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
---
target/riscv/csr.c | 15 +++
1
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
If smstateen is implemented and smtateen0.fcsr is clear and misa.F
is off then the floating point operations must return illegal
instruction exception or virtual instruction trap, if relevant.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
---
target/riscv/csr.c | 15 +++
1
When misa.F is 0 tb->flags.FS field is unused and can be used to save
the current state of smstateen0.FCSR check which is needed by the
floating point translation routines.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
---
target/riscv/cpu_helper.c | 6 ++
tar
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
smstateen_fcsr_check to function
- Add fcsr check for zdinx
Mayuresh Chitale (3):
target/riscv: smstateen check for fcsr
target/riscv: Reuse tb->flags.FS
target/riscv: smstateen knobs
target/riscv/cpu.c | 3 ++-
target/riscv/cpu_helper.c | 6 ++
target/ri
Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec
and check for it when accessing the fcsr register and its fields.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
---
target/riscv/csr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/riscv
When misa.F is 0 tb->flags.FS field is unused and can be used to save
the current state of smstateen0.FCSR check which is needed by the
floating point translation routines.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
---
target/riscv/cpu_helpe
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
description
- Reuse TB_FLAGS.HS_FS for smstateen
- Convert smstateen_fcsr_check to function
- Add fcsr check for zdinx
Mayuresh Chitale (3):
target/riscv: smstateen check for fcsr
target/riscv: Reuse tb->flags.FS
target/riscv: smstateen knobs
target/riscv/cpu.c |
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2
Changes in v2:
- Make h/s/envcfg bits in m/h/stateen registers as writeable by default.
Mayuresh Chitale (4):
target/riscv: Add smstateen support
target/riscv: smstateen check for h/senvcfg
target/riscv: smstateen check for fcsr
target/riscv: smstateen check for AIA/IMSIC
target/riscv/cpu.c
If smstateen is implemented and sstateen0.fcsr is clear
then the floating point operations must return illegal
instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/riscv/csr.c b/target
Accesses to henvcfg, henvcfgh and senvcfg are allowed
only if corresponding bit in mstateen0/hstateen0 is
enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 84 ++
1 file changed, 78
If smstateen is implemented then accesses to AIA
registers CSRS, IMSIC CSRs and other IMSIC registers
is controlled by setting of corresponding bits in
mstateen/hstateen registers. Otherwise an illegal
instruction trap or virtual instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.
Signed-off-by: Mayuresh Chitale
---
target/riscv/translate.c | 9 -
1 file changed, 8 insertions(+), 1 deletion
isa_edata_arr as
described in rule #3 the comment.
Changes in v4:
- Fix build issue with riscv32/riscv64-linux-user targets
Changes in v3:
- Fix coding style issues
- Fix *stateen0h index calculation
Changes in v2:
- Make h/s/envcfg bits in m/h/stateen registers as writeable by default.
Mayuresh
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
---
target
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding
bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 87
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv
If smstateen is implemented and sstateen0.fcsr is clear then the floating point
operations must return illegal instruction exception or virtual instruction
trap, if relevant.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c| 23
target/riscv/insn_trans
Set the state of each ISA extension on the vcpu depending on what
is set in the CPU property and what is allowed by KVM for that extension.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 11 -
target/riscv/kvm.c | 88 ++--
target
extensions from the list of single letter extensions as those are not
supported yet.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 41 +++--
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cp
Currently the single and multi letter ISA extensions exposed to the guest
vcpu don't confirm to the KVM policies. This patchset updates the kvm headers
and applies policies set in KVM to the extensions exposed to the guest.
Mayuresh Chitale (3):
update-linux-headers: Version 6.1-rc2
t
Sync headers with kernel commit 247f34f7b803
Signed-off-by: Mayuresh Chitale
---
include/standard-headers/drm/drm_fourcc.h | 34 -
include/standard-headers/linux/ethtool.h | 63 +++-
include/standard-headers/linux/fuse.h | 6 +-
.../linux/input-event-codes.h
https://github.com/mdchitale/qemu.git
Changes in v3:
- Address comments from Bin Meng
Changes in v2:
- Rebase to latest riscv-to-apply.next
- Update linux headers to version 6.1-rc8
- Add reviewed by tags
Mayuresh Chitale (3):
update-linux-headers: Version 6.1-rc8
target/riscv: Extend isa_ext_dat
Sync headers with kernel commit 76dcd734eca2
Signed-off-by: Mayuresh Chitale
Reviewed-by: Andrew Jones
---
include/standard-headers/drm/drm_fourcc.h | 34 -
include/standard-headers/linux/ethtool.h | 63 +++-
include/standard-headers/linux/fuse.h | 6 +-
.../linux
Set the state of each ISA extension on the vcpu depending on what
is set in the CPU property and what is allowed by KVM for that extension.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 11 -
target/riscv/kvm.c
extensions from the list of single letter extensions as those are not
supported yet.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 41 +++--
1 file changed, 23 inserti
On Thu, 2022-06-16 at 15:48 +1000, Alistair Francis wrote:
> On Sat, Jun 4, 2022 at 2:13 AM Mayuresh Chitale
> wrote:
> > Smstateen extension specifies a mechanism to close
> > the potential covert channels that could cause security issues.
> >
> > This patc
On Thu, 2022-06-16 at 17:17 +1000, Alistair Francis wrote:
> On Sat, Jun 4, 2022 at 2:08 AM Mayuresh Chitale
> wrote:
> > If smstateen is implemented and sstateen0.fcsr is clear
> > then the floating point operations must return illegal
> > instruction exception.
> >
On Thu, 2022-06-16 at 17:18 +1000, Alistair Francis wrote:
> On Sat, Jun 4, 2022 at 2:15 AM Mayuresh Chitale
> wrote:
> > If smstateen is implemented then accesses to AIA
> > registers CSRS, IMSIC CSRs and other IMSIC registers
> > is controlled by setting of correspond
On Sat, 2022-07-02 at 18:19 +0800, angell1518 wrote:
> At 2022-06-04 00:04:22, "Mayuresh Chitale" > wrote:
> >Smstateen extension specifies a mechanism to close
> >the potential covert channels that could cause security issues.
> >
> >This patch adds t
On Sat, 2022-07-02 at 18:33 +0800, angell1518 wrote:
> At 2022-06-04 00:04:23, "Mayuresh Chitale" > wrote:
> >Accesses to henvcfg, henvcfgh and senvcfg are allowed
> >only if corresponding bit in mstateen0/hstateen0 is
> >enabled. Otherwise an illega
On Fri, 2022-07-08 at 07:44 +0800, Weiwei Li wrote:
> 在 2022/7/8 上午12:53, Mayuresh Chitale 写道:
> > On Sat, 2022-07-02 at 18:19 +0800, angell1518 wrote:
> > > At 2022-06-04 00:04:22, "Mayuresh Chitale" <
> > > mchit...@ventanamicro.com
> > >
Patel (1):
target/riscv: Force disable extensions if priv spec version does not
match
*** BLURB HERE ***
Mayuresh Chitale (5):
target/riscv: Add smstateen support
target/riscv: smstateen check for h/senvcfg
target/riscv: smstateen check for fcsr
target/riscv: smstateen check for AIA
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.h | 4
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if
corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an
illegal instruction trap is generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 100 +
1 file changed, 93
If smstateen is implemented and sstateen0.fcsr is clear then the
floating point operations must return illegal instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c| 23 ++
target/riscv/insn_trans/trans_rvf.c.inc | 38
If smstateen is implemented then accesses to AIA
registers CSRS, IMSIC CSRs and other IMSIC registers
is controlled by setting of corresponding bits in
mstateen/hstateen registers. Otherwise an illegal
instruction trap or virtual instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db2b8e4d30..2b7ed95396 100644
--- a/target
If smstateen is implemented and sstateen0.fcsr is clear
then the floating point operations must return illegal
instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/riscv/csr.c b/target
writeable by default.
Anup Patel (1):
target/riscv: Force disable extensions if priv spec version does not
match
Mayuresh Chitale (4):
target/riscv: Add smstateen support
target/riscv: smstateen check for h/senvcfg
target/riscv: smstateen check for fcsr
target/riscv: smstateen check for
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2
If smstateen is implemented then accesses to AIA
registers CSRS, IMSIC CSRs and other IMSIC registers
is controlled by setting of corresponding bits in
mstateen/hstateen registers. Otherwise an illegal
instruction trap or virtual instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
Accesses to henvcfg, henvcfgh and senvcfg are allowed
only if corresponding bit in mstateen0/hstateen0 is
enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 84 ++
1 file changed, 78
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2
Accesses to henvcfg, henvcfgh and senvcfg are allowed
only if corresponding bit in mstateen0/hstateen0 is
enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 70 --
1 file changed, 68
If smstateen is implemented and sstateen0.fcsr is clear
then the floating point operations must return illegal
instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/riscv/csr.c b/target
controlled via smstateen.
This series depends on the following series from Atish Patra:
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00031.html
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00142.html
Mayuresh Chitale (4):
target/riscv: Add smstateen support
target/riscv
If smstateen is implemented then accesses to AIA
registers CSRS, IMSIC CSRs and other IMSIC registers
is controlled by setting of corresponding bits in
mstateen/hstateen registers. Otherwise an illegal
instruction trap or virtual instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
writeable by default.
Mayuresh Chitale (4):
target/riscv: Add smstateen support
target/riscv: smstateen check for h/senvcfg
target/riscv: smstateen check for fcsr
target/riscv: smstateen check for AIA/IMSIC
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 4 +
target/riscv/cpu_bits.h
Smstateen extension specifies a mechanism to close
the potential covert channels that could cause security issues.
This patch adds the CSRs defined in the specification and
the corresponding predicates and read/write functions.
Signed-off-by: Mayuresh Chitale
---
target/riscv/cpu.c | 2
Accesses to henvcfg, henvcfgh and senvcfg are allowed
only if corresponding bit in mstateen0/hstateen0 is
enabled. Otherwise an illegal instruction trap is
generated.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 82 ++
1 file changed, 76
If smstateen is implemented and sstateen0.fcsr is clear
then the floating point operations must return illegal
instruction exception.
Signed-off-by: Mayuresh Chitale
---
target/riscv/csr.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/riscv/csr.c b/target
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