[RFC PATCH 2/4] target/riscv: Add fcsr field in tb->flags

[Mayuresh Chitale]

The state of smstateen0.FCSR bit impacts the execution of floating point
instructions when misa.F==0. Add a field in the tb->flags which stores
the current state of smstateen0.fcsr and will be used by floating point
translation routines.

Signed-off-by: Mayuresh Chitale <mchit...@ventanamicro.com>
---
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu_helper.c | 5 +++++
 target/riscv/translate.c  | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 132cf06ff2..9c6b10d29a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -653,6 +653,7 @@ FIELD(TB_FLAGS, VTA, 24, 1)
 FIELD(TB_FLAGS, VMA, 25, 1)
 /* Native debug itrigger */
 FIELD(TB_FLAGS, ITRIGGER, 26, 1)
+FIELD(TB_FLAGS, FCSR, 27, 1)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f88c503cf4..1590e6e480 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -117,6 +117,11 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong 
*pc,
     if (env->cur_pmbase != 0) {
         flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
     }
+    if (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) {
+        flags = FIELD_DP32(flags, TB_FLAGS, FCSR, 1);
+    } else {
+        flags = FIELD_DP32(flags, TB_FLAGS, FCSR, 0);
+    }
 
     *pflags = flags;
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0ee8ee147d..4880eaeb89 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -77,6 +77,7 @@ typedef struct DisasContext {
     int frm;
     RISCVMXL ol;
     bool virt_inst_excp;
+    bool smstateen_fcsr_ok;
     bool virt_enabled;
     const RISCVCPUConfig *cfg_ptr;
     bool hlsx;
@@ -1187,6 +1188,7 @@ static void riscv_tr_init_disas_context(DisasContextBase 
*dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->smstateen_fcsr_ok = FIELD_EX32(tb_flags, TB_FLAGS, FCSR);
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.34.1