On Mon, Apr 10, 2023 at 8:14 PM liweiwei <liwei...@iscas.ac.cn> wrote:
>
>
> On 2023/4/10 22:13, Mayuresh Chitale wrote:
> > If smstateen is implemented and sstateen0.fcsr is clear then the
> > floating point operations must return illegal instruction exception
> > or virtual instruction trap, if relevant.
>
> typo. sstateen0 -> smstateen
Ok.
>
> And fcsr bit only work when F is not enabled.
Will fix it.
>
> >
> > Signed-off-by: Mayuresh Chitale <mchit...@ventanamicro.com>
> > ---
> > target/riscv/cpu.h | 3 +++
> > target/riscv/csr.c | 25 ++++++++++++++++++++++++-
> > 2 files changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 638e47c75a..132cf06ff2 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -613,6 +613,9 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env,
> > uint32_t priv,
> > target_ulong new_val,
> > target_ulong write_mask),
> > void *rmw_fn_arg);
> > +RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t
> > bit);
> This have been added in the latest riscv-to-apply.next.
> > +#else
> > +#define smstateen_acc_ok(env, index, bit) RISCV_EXCP_NONE
>
> This seems unnecessary. smstateen_acc_ok in this patch works only in
> system mode.
Ok.
>
> Regards,
>
> Weiwei Li
>
> > #endif
> > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index d522efc0b6..4979058434 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -43,7 +43,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations
> > *ops)
> >
> > /* Predicates */
> > #if !defined(CONFIG_USER_ONLY)
> > -static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
> > +RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
> > uint64_t bit)
> > {
> > bool virt = riscv_cpu_virt_enabled(env);
> > @@ -83,6 +83,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> > !riscv_cpu_cfg(env)->ext_zfinx) {
> > return RISCV_EXCP_ILLEGAL_INST;
> > }
> > +
> > + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> > + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
> > + }
> > #endif
> > return RISCV_EXCP_NONE;
> > }
> > @@ -2056,6 +2060,9 @@ static RISCVException write_mstateen0(CPURISCVState
> > *env, int csrno,
> > target_ulong new_val)
> > {
> > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> > + if (!riscv_has_ext(env, RVF)) {
> > + wr_mask |= SMSTATEEN0_FCSR;
> > + }
> >
> > return write_mstateen(env, csrno, wr_mask, new_val);
> > }
> > @@ -2092,6 +2099,10 @@ static RISCVException write_mstateen0h(CPURISCVState
> > *env, int csrno,
> > {
> > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >
> > + if (!riscv_has_ext(env, RVF)) {
> > + wr_mask |= SMSTATEEN0_FCSR;
> > + }
> > +
> > return write_mstateenh(env, csrno, wr_mask, new_val);
> > }
> >
> > @@ -2129,6 +2140,10 @@ static RISCVException write_hstateen0(CPURISCVState
> > *env, int csrno,
> > {
> > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >
> > + if (!riscv_has_ext(env, RVF)) {
> > + wr_mask |= SMSTATEEN0_FCSR;
> > + }
> > +
> > return write_hstateen(env, csrno, wr_mask, new_val);
> > }
> >
> > @@ -2168,6 +2183,10 @@ static RISCVException write_hstateen0h(CPURISCVState
> > *env, int csrno,
> > {
> > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >
> > + if (!riscv_has_ext(env, RVF)) {
> > + wr_mask |= SMSTATEEN0_FCSR;
> > + }
> > +
> > return write_hstateenh(env, csrno, wr_mask, new_val);
> > }
> >
> > @@ -2215,6 +2234,10 @@ static RISCVException write_sstateen0(CPURISCVState
> > *env, int csrno,
> > {
> > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> >
> > + if (!riscv_has_ext(env, RVF)) {
> > + wr_mask |= SMSTATEEN0_FCSR;
> > + }
> > +
> > return write_sstateen(env, csrno, wr_mask, new_val);
> > }
> >
>
