Re: [PATCH 02/12] target/riscv: handle vrgather mask and source overlap

Hi Anton, You might need to extend this patch or provide a new patch to handle the different EEWs source operands checking for the vrgatherei16.vv instruction (when SEW is not 16). Thanks, Max On 2025/1/26 3:20 PM, Anton Blanchard wrote: Signed-off-by: Anton Blanchard --- target/riscv/insn

Re: [PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap

Hi Anton, I think that the commit message could be improved for better clarity. The vext_check_ss function affects more RVV instructions than the vadd.vx instruction alone. (PS:perhaps using the category (OPIVX/OPFVF/etc.) to describe the affected RVV instructions would be more helpful.) Addit

Re: [PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap

Hi Anton, The vext_check_slide function affects the vslide[up|down].v[x|i]/vfslide1[up|down].vf/vslide1[up|down].vx instructions than the vslide1down.vx instruction alone. Therefore, it would be more appropriate to update the commit message to provide a clearer information. (PS:perhaps, using

Re: [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

Hi Anton, This patch violates some coding style rules of QEMU. You can verify the coding style by running the checkpatch.pl script in the QEMU repository. (ref: https://www.qemu.org/docs/master/devel/submitting-a-patch.html#use-the-qemu-coding-style) The patch 12 also has the same issue. Than

Re: [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

Reviewed-by: Max Chou On 2025/1/26 3:20 PM, Anton Blanchard wrote: Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

Re: [PATCH v7 2/2] target/riscv: rvv: speed up small unit-stride loads and stores

On 2024/12/11 8:51 PM, Craig Blackmore wrote: Calling `vext_continuous_ldst_tlb` for load/stores smaller than 12 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: P

Re: [PATCH v8 1/2] target/riscv: rvv: fix typo in vext continuous ldst function names

Reviewed-by: Max Chou max On 2024/12/18 10:23 PM, Craig Blackmore wrote: Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/vector_helper.c b

Re: [RFC 1/1 v2] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

+for (int i = 0; i < size; i += 16) { +addr = get_address(s, rs1, i); +if (is_load) { +tcg_gen_qemu_ld_i128(t16, addr, s->mem_idx, +MO_LE | MO_128 | atomicity); +tcg_gen_st_i128(t16, tcg_env, vreg_ofs(s, vd) +

[PATCH] target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64

value to 64 bits during the TCG translation phase to ensure that the helper functions won't lost the higer 32 bits. Signed-off-by: Max Chou --- target/riscv/helper.h | 16 target/riscv/insn_trans/trans_rvv.c.inc | 50 - target/

[PATCH] target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set

In prop_vlen_set function, there is an incorrect comparison between vlen(bit) and vlenb(byte). This will cause unexpected error when user applies the `vlen=1024` cpu option with a vendor predefined cpu type that the default vlen is 1024(vlenb=128). Signed-off-by: Max Chou --- target/riscv/cpu.c

[PATCH] target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0

According to the Vector Reduction Operations section in the RISC-V "V" Vector Extension spec, "If vl=0, no operation is performed and the destination register is not updated." The vd should be updated when vl is larger than 0. Signed-off-by: Max Chou --- target/riscv

[PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint

According to the v spec, a vector register cannot be used to provide source operands with more than one EEW for a single instruction. Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 29 + 1 file changed, 29 insertions(+) diff --git a/target/riscv

[PATCH v3 09/10] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH v3 03/10] target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched input EEWs encoding constraint

According to the v spec, a vector register cannot be used to provide source operands with more than one EEW for a single instruction. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans

[PATCH v3 08/10] target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions

Handle the overlap of source registers with different EEWs. The vd of vector widening mul-add instructions is one of the input operands. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvbf16.c.inc | 9 ++- target

[PATCH v3 07/10] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v3 02/10] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

From: Anton Blanchard Signed-off-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v3 04/10] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v3 10/10] target/riscv: Fix the rvv reserved encoding of unmasked instructions

According to the v spec, the encodings of vcomoress.vm and vector mask-register logical instructions with vm=0 are reserved. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn32.decode | 18 +- 1 file changed, 9 insertions(+), 9 deletions

[PATCH v3 05/10] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b

[PATCH v3 06/10] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v3 01/10] target/riscv: rvv: Source vector registers cannot overlap mask register

From: Anton Blanchard Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans

[PATCH v3 00/10] Fix RVV encoding corner cases

estions and review. Anton Blanchard (2): target/riscv: rvv: Source vector registers cannot overlap mask register target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS Max Chou (8): target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched i

Re: [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint

On 2025/4/5 5:09 PM, Daniel Henrique Barboza wrote: On 3/29/25 11:44 AM, Max Chou wrote: According to the v spec, a vector register cannot be used to provide source operands with more than one EEW for a single instruction. Signed-off-by: Max Chou ---   target/riscv/insn_trans

Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

On 2025/4/5 5:14 PM, Daniel Henrique Barboza wrote: On 3/29/25 11:44 AM, Max Chou wrote: Handle the overlap of source registers with different EEWs. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Since you're marked as Author you don&#

Re: [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

On 2025/4/5 5:17 PM, Daniel Henrique Barboza wrote: On 3/29/25 11:44 AM, Max Chou wrote: Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou ---   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-   1

Re: [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

Hi Anton, I hope you’re doing well. While reviewing this patchset, I noticed a few missing parts related to the mismatched input EEWs encoding constraint. I also found a few other rvv encoding issues and planned to submit an upstream patchset to address them. However, I think it would be bette

[PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register

From: Anton Blanchard Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--- 1 file changed, 26

[PATCH v2 00/12] Fix RVV encoding corner cases

andling of register overlaps in vector widening/narrowing instructions 4. Fix unmasked RVV instruction encoding (e.g. vcompress.vm) Anton Blanchard (2): target/riscv: rvv: Source vector registers cannot overlap mask register target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS Ma

[PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

From: Anton Blanchard Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions

According to the v spec, the encodings of vcomoress.vm and vector mask-register logical instructions with vm=0 are reserved. Signed-off-by: Max Chou --- target/riscv/insn32.decode | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b

[PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.)

Handle the overlap of source registers with different EEWs. The vd of vector widening mul-add instructions is one of the input operands. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvbf16.c.inc | 9 ++- target/riscv

[PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

Handle the overlap of source registers with different EEWs. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv

[PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Co-authored-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

Re: [PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

Hi Nutty, Thanks for the suggestion. I'll provide a new version including the new description and a fix about another EEWs issue. Thanks, Max On Tue, Jul 1, 2025 at 2:43 PM Nutty Liu wrote: > On 6/27/2025 9:20 PM, Max Chou wrote: > > From: Anton Blanchard > > >

Re: [PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions

On 6/27/25 10:21 AM, Max Chou wrote: > > According to the RISC-V instruction set manual, the minimum VLEN needs > > to respect the following extensions: > > > >Extension Minimum VLEN > > * V 128 > > * Zve64[d|f|x] 64 > > * Zve32[f|x

[PATCH v2 3/3] target/riscv: vadc and vsbc are vm=0 instructions

From: Anton Blanchard We were marking vadc and vsbc as vm=1 instructions, which meant vext_check_input_eew wouldn't detect mask vs source register overlaps. Signed-off-by: Anton Blanchard Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn32.decode | 10 +- 1

[PATCH v2 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp compare instructions

From: Anton Blanchard Handle the overlap of source registers with different EEWs. Signed-off-by: Anton Blanchard Reviewed-by: Max Chou Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff

[PATCH v2 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions

From: Anton Blanchard Handle the overlap of source registers with different EEWs. Signed-off-by: Anton Blanchard Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions

According to the RISC-V instruction set manual, the minimum VLEN needs to respect the following extensions: Extension Minimum VLEN * V 128 * Zve64[d|f|x] 64 * Zve32[f|x] 32 Signed-off-by: Max Chou --- target/riscv/tcg/tcg-cpu.c | 13 +++-- 1 file changed, 11

[PATCH] target/riscv: rvv: Fix missing exit TB flow for ldff_trans

According to the V spec, the vector fault-only-first load instructions may change the VL CSR. So the ldff_trans TCG translation function should generate the lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to make sure the vl_eq_vlmax TB flag is correct. Signed-off-by: Max Chou

[PATCH v2 0/3] Fix some more RVV source overlap issues

This patchset is based on the v1 provided by Anoton Blanchard with following update: * Add the missing input EEWs checking rule for widen vector reduction instruction. Reference: * v1: 20250415043207.3512209-1-ant...@tenstorrent.com Anton Blanchard (3): target/riscv: rvv: Apply vext_check_in

[PATCH v4 17/17] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties

From: Nazar Kazakov Exposes earlier CPU flags allowing the use of the vector cryptography extensions. Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou --- target/riscv/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

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