Add multiprocess extension support by enabling multiprocess mode when
the peer requests it, and by replying that we actually support it in the
qSupported reply packet.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Create two separate CPU clusters for APUs and RPUs.
Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-zynqmp.h | 3 +++
hw/arm/xlnx-zynqmp.c | 21 +
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/include/hw/arm/xlnx
Change the thread info related packets handling to support multiprocess
extension.
Add the CPUs class name in the extra info to help differentiate
them in multiprocess mode.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
---
gdbstub.c | 37
by the peer.
This function supports the multiprocess extension thread-id syntax. The
return value specifies if the parsing failed, or if a special case was
encountered (all processes or all threads).
Use them in 'H' and 'T' packets handling to support the multiprocess
extension.
On 11/29/18 5:36 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Remove bogus virtio-mmio creation. This was an accidental
> left-over an experiment.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
Luc
> ---
> hw/arm/xlnx-versal
On 11/30/18 5:52 PM, Peter Maydell wrote:
> On Mon, 26 Nov 2018 at 13:27, Eduardo Habkost wrote:
>>
>> On Sun, Nov 25, 2018 at 10:27:04PM +0100, Philippe Mathieu-Daudé wrote:
>>> Hi Eduardo,
>>>
>>> On 23/11/18 19:10, Eduardo Habkost wrote:
If you really want to do this and assign cluster_id
On 12/3/18 12:23 PM, Peter Maydell wrote:
> On Mon, 3 Dec 2018 at 11:21, Luc Michel wrote:
>>
>> On 11/30/18 5:52 PM, Peter Maydell wrote:
>>> Luc: what are the requirements on boards using CPU cluster
>>> objects? I assume these are both OK:
>>&
Hi all,
What do you think of this re-roll? Is it in good shape for upstreaming?
Thanks!
--
Luc
On 12/7/18 10:01 AM, Luc Michel wrote:
> changes since v7:
> - patch 1Add documentation about cpu-cluster [Eduardo, Peter]
>
> - patch 1Remove the cluster-id auto-assi
istent.
When PID is specified but TID is 0, the function returns the first CPU
in the process, or NULL if the process does not exist or is not
attached.
In other cases, it returns the corresponding CPU, while ignoring the PID
check when PID is 0.
Reported-by: Peter Maydell
Signed-off-by: Luc Mi
On 1/18/19 12:22 PM, Philippe Mathieu-Daudé wrote:
> The "Hg" GDB packet is used to select the current thread, and can fail.
> GDB doesn't not check for failure and emits further packets that can
> access and dereference s->c_cpu or s->g_cpu.
>
> Add a check that returns "E22" (EINVAL) when those
On 1/4/19 3:28 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Create an unimplemented GPIO area instead of leaving it unassigned.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/microblaze/petalogix_s3adsp1800_mmu.
On 1/4/19 3:28 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add MicroBlaze CPU properties to enable exceptions on failed
> bus accesses.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> target/microblaze/cpu.c | 12 +
On 1/4/19 4:12 PM, Peter Maydell wrote:
> On Fri, 7 Dec 2018 at 09:01, Luc Michel wrote:
>> This series adds support for the multiprocess extension of the GDB
>> remote protocol in the QEMU GDB stub.
>>
>> This extension is useful to split QEMU emulated CPUs in diff
child objects are added, so move
> the realize of rpu_cluster. (The apu_cluster is already
> realized after child population.)
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-zynqmp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
s one.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> include/hw/cpu/cluster.h | 19 +++
> include/qom/cpu.h| 7 +++
> hw/cpu/cluster.c | 33 +
> qom/cpu.c| 1 +
> 4
d
> more bits in cflags for other purposes, we could make
> tb_hash_func() take more data (and expand qemu_xxhash7()
> to qemu_xxhash8()).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> include/exec/exec-all.h | 4 +++-
> accel/tcg/cpu-exec.c | 4 +++
On 1/8/19 5:30 PM, Peter Maydell wrote:
> Now we're keeping the cluster index in the CPUState, we don't
> need to jump through hoops in gdb_get_cpu_pid() to find the
> associated cluster object.
Aah better :-)
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
gt; should
> + *implement the virtualization extensions
> + * + unnamed GPIO inputs: (where P is number of PPIs, i.e. num-irq - 32)
I think here it's "where P is the number of SPIs".
Apart from that:
Reviewed-by: Luc Michel
--
Luc
> + *[0..P-1] SPI
Add support for the '!' extended mode packet. This is required for the
multiprocess extension.
Signed-off-by: Luc Michel
---
gdbstub.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index af8864e251..4bed0a85f3 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@
by the peer.
This function supports the multiprocess extension thread-id syntax. The
return value specifies if the parsing failed, or if a special case was
encountered (all processes or all threads).
Use them in 'H' and 'T' packets handling to support the multiprocess
extension.
Add support for the vAttach packets. In multiprocess mode, GDB sends
them to attach to additional processes.
Signed-off-by: Luc Michel
---
gdbstub.c | 32
1 file changed, 32 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index 4bed0a85f3..4874d65a30 100644
Add support for multiprocess extension in gdb_vm_state_change()
function.
Signed-off-by: Luc Michel
---
gdbstub.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 761cb051c8..4ccd1153ce 100644
--- a/gdbstub.c
+++ b/gdbstub.c
Change the thread info related packets handling to support multiprocess
extension.
Add the CPUs class name in the extra info to help differentiate
them in multiprocess mode.
Signed-off-by: Luc Michel
---
gdbstub.c | 32 ++--
1 file changed, 22 insertions(+), 10
Change the sC packet handling to support the multiprocess extension.
Instead of returning the first thread, we return the first thread of the
current process.
Signed-off-by: Luc Michel
---
gdbstub.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/gdbstub.c b
a
parameter, and use a buffer in the process structure to store the
generated description.
It takes the first CPU of the process to generate the description.
Signed-off-by: Luc Michel
---
gdbstub.c | 44
1 file changed, 24 insertions(+), 20 deletions
When a new connection is established, we set the first process to be
attached, and the others detached. The first CPU of the first process
is selected as the current CPU.
Signed-off-by: Luc Michel
---
gdbstub.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff
Create two separate QOM containers for APUs and RPUs to indicate to the
GDB stub that those CPUs should be put in different processes.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-zynqmp.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx
When gdb_set_stop_cpu() is called with a CPU associated to a process
currently not attached by the GDB client, return without modifying the
stop CPU. Otherwise, GDB get confused if it receives packets with a
thread-id it does not know about.
Signed-off-by: Luc Michel
---
gdbstub.c | 9
?' request.
Signed-off-by: Luc Michel
---
gdbstub.c | 46 --
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 5c86218f49..ec3105dbc1 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -640,10 +640,37 @@ static int m
ation and their prototype implementation.
Luc Michel (15):
gdbstub: introduce GDB processes
gdbstub: add multiprocess support to '?' packets
gdbstub: add multiprocess support to 'H' and 'T' packets
gdbstub: add multiprocess support to vCont packets
gdbst
esses do not make much sense for now.
Signed-off-by: Luc Michel
---
include/exec/gdbstub.h | 8 +
gdbstub.c | 67 ++
2 files changed, 75 insertions(+)
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 08363969c1..a3e41
Add the gdb_first_cpu() and gdb_next_cpu() to iterate over all
the CPUs in currently attached processes.
Add the gdb_first_cpu_in_process() and gdb_next_cpu_in_process() to
iterate over CPUs of a given process.
Use them to add multiprocess extension support to vCont packets.
Signed-off-by: Luc
Add multiprocess extension support by enabling multiprocess mode when
the peer requests it, and by replying that we actually support it in the
qSupported reply packet.
Signed-off-by: Luc Michel
---
gdbstub.c | 4
1 file changed, 4 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index
'D' packets are used by GDB to detach from a process. In multiprocess
mode, the PID to detach from is sent in the request.
Signed-off-by: Luc Michel
---
gdbstub.c | 55 ---
1 file changed, 48 insertions(+), 7 deletions(-)
di
On 8/24/18 6:18 PM, Peter Maydell wrote:
> The GIC_BASE_IRQ macro is a leftover from when we shared code
> between the GICv2 and the v7M NVIC. Since the NVIC is now
> split off, GIC_BASE_IRQ is always 0, and we can just delete it.
>
> Signed-off-by: Peter Maydell
Reviewed
On 07/05/2018 10:00 AM, Jan Kiszka wrote:
> On 2018-07-05 08:51, Jan Kiszka wrote:
>> On 2018-06-29 15:29, Luc Michel wrote:
>>> Add support for GICv2 virtualization extensions by mapping the necessary
>>> I/O regions and connecting the maintenance IRQ lines.
>>
nly from irq_state[] into the following
> irq_target[] array which the guest can already manipulate.
>
> Signed-off-by: Peter Maydell
> ---
> hw/intc/arm_gic.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
Reviewed-by: Luc Michel
--
Luc
signature.asc
Description: OpenPGP digital signature
0 for IRQs 0..28 unless this
> is an 11MPCore GIC.
>
> Reported-by: Jan Kiszka
> Signed-off-by: Peter Maydell
> ---
> hw/intc/arm_gic.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Luc Michel
--
Luc
signature.asc
Description: OpenPGP digital signature
On 07/12/2018 03:56 PM, Peter Maydell wrote:
> On 29 June 2018 at 14:29, Luc Michel wrote:
>> Add the gic_update_virt() function to update the vCPU interface states
>> and raise vIRQ and vFIQ as needed. This commit renames gic_update() to
>> gic_update_internal() and gen
On 07/12/2018 03:37 PM, Peter Maydell wrote:
> On 29 June 2018 at 14:29, Luc Michel wrote:
>> Add the read/write functions to handle accesses to the vCPU interface.
>> Those accesses are forwarded to the real CPU interface, with the CPU id
>> being converted to the corres
Fix Memory region size for GICv2 virtual interface and
vCPU iface. [Peter]
Luc Michel (20):
intc/arm_gic: Refactor operations on the distributor
intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers
intc/arm_gic: Remove some dead code and put some functions static
vmstate.
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 23
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 61 +++
1 file changed, 57 insertions(+), 4
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/gic_internal.h | 65 ++
1 file changed, 65 insertions(+)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index
tributor is not
exposed to vCPUs at all.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 39 ++-
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1ac0fe740c..53cc257ed8 1006
virtual interface, in h_apr.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 50 +++
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index ad241d12c2..60704cabbb 100644
--- a/hw/intc/arm_gic.c
+++ b
-by: Luc Michel
---
hw/intc/arm_gic.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index be9e2594d9..50cbbfbe24 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -590,6 +590,15 @@ static void gic_deactivate_irq(GICState *s, int
Implement the maintenance interrupt generation that is part of the GICv2
virtualization extensions.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/hw/intc/arm_gic.c
given (vCPU, irq) pair. It
is meant to be used in contexts where we know for sure that the entry
exists, so we assert that entry is actually found, and the caller can
avoid the NULL check on the returned pointer.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 5 +++
hw/intc/gic_internal.h
case in gic_clear_pending_sgi() to enhance
code readability as the virtualization extensions support adds a if-else
level.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 52 ++-
1 file changed, 33 insertions(+), 19 deletions
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off-by: Luc Michel
Add support for GICv2 virtualization extensions by mapping the necessary
I/O regions and connecting the maintenance IRQ lines.
Declare those additions in the device tree and in the ACPI tables.
Signed-off-by: Luc Michel
---
hw/arm/virt-acpi-build.c | 6 +++--
hw/arm/virt.c| 52
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 20 +++-
1
generation.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c| 31 +--
hw/intc/trace-events | 12 ++--
2 files changed, 35 insertions(+), 8 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw
effect on the distributor, even in the
vCPU case, when the correponding LR has the HW field set.
Use those functions in the CPU interface code path to prepare for the
vCPU interface implementation.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 32 +++-
hw/intc/gic_internal.h | 83
fetches the current vCPU id using the current_cpu global variable, and
one mirror region per vCPU which maps to that specific vCPU id. This is
required by the GIC architecture specification.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 37 +++--
1 file changed
information.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-zynqmp.c | 92
include/hw/arm/xlnx-zynqmp.h | 4 +-
2 files changed, 86 insertions(+), 10 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 29df35fb75..42c29b8d06 100644
Implement the read and write functions for the virtual interface of the
virtualization extensions in the GICv2.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 235 +-
1 file changed, 233 insertions(+), 2 deletions
implement
the virtualization extensions, we report an error if the corresponding
property is set to true.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c| 2 +-
hw/intc/arm_gic_common.c | 148 ++-
hw/intc/arm
The main difference between CPU and vCPU is the way we select the best
IRQ. This part has been split into the gic_get_best_(v)irq functions.
For the virt case, the LRs are iterated to find the best candidate.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c
On 07/17/2018 03:32 PM, Peter Maydell wrote:
> On 14 July 2018 at 18:15, Luc Michel wrote:
>> Implement virtualization extensions in the gic_deactivate_irq() and
>> gic_complete_irq() functions. When a guest tries to deactivat or end an
>
> "deactivate"
>
On 07/17/2018 04:26 PM, Peter Maydell wrote:
> On 14 July 2018 at 18:15, Luc Michel wrote:
>> Add the read/write functions to handle accesses to the vCPU interface.
>> Those accesses are forwarded to the real CPU interface, with the CPU id
>> being converted to the correspon
From: Luc MICHEL
This commit improve the way the GIC is realized and connected in the
ZynqMP SoC. The security extensions are enabled only if requested in the
machine state. The same goes for the virtualization extensions.
All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ
From: Luc MICHEL
Add some traces to the ARM GIC to catch register accesses (distributor,
(v)cpu interface and virtual interface), and to take into account
virtualization extensions (print `vcpu` instead of `cpu` when needed).
Also add some virtualization extensions specific traces: LR updating
From: Luc MICHEL
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc MICHEL
---
hw/intc/arm_gic.c | 23 ++-
hw/intc/gic_internal.h | 4
From: Luc MICHEL
Add the necessary parts of the virtualization extensions state to the
GIC state. We choose to increase the size of the CPU interfaces state to
add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way,
we'll be able to reuse most of the CPU interface code fo
From: Luc MICHEL
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off
From: Luc MICHEL
This commit adds the actual implementation of the GICv2 virtualization
extensions logic.
For the vCPU interfaces, most of the existing CPU interface code is
reused. Calls to macros or functions modifying the distributor state are
replaced with equivalent generic inline
From: Luc MICHEL
This patch series add support for the virtualization extensions in the
ARM GICv2 interrupt controller.
The first two commits do some refactoring to prepare for the
implementation. Commits 3 and 4 are the actual implementation. The last
commit updates the ZynqMP implementation
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 23
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index
Implement the maintenance interrupt generation that is part of the GICv2
virtualization extensions.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/hw/intc/arm_gic.c
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/gic_internal.h | 65 ++
1 file changed, 65 insertions(+)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
ite to V_DIR increments V_HCR.EOICount.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 51 +++
1 file changed, 47 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d80acde989..3cddf65826 100644
--- a/hw/intc/arm_gi
given (vCPU, irq) pair. It
is meant to be used in contexts where we know for sure that the entry
exists, so we assert that entry is actually found, and the caller can
avoid the NULL check on the returned pointer.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 5
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 61 +++
1 file
thesises. See commit message for the adopted behaviour.
The main difference is that when EOIMode is true (EOI split is
enabled), a write to V_EOIR never increments H_HCR.EOICount. [Peter]
- Patch 14-15: fixed commit message regarding mirrored regions. [Peter]
Luc Michel (20):
intc/arm_gic: Re
tributor is not
exposed to vCPUs at all.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 39 ++-
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 41141fee53..94d5982e2a 1006
virtual interface, in h_apr.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 50 +++
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 26ed7ea58a..de73dc9f54 100644
The main difference between CPU and vCPU is the way we select the best
IRQ. This part has been split into the gic_get_best_(v)irq functions.
For the virt case, the LRs are iterated to find the best candidate.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c
case in gic_clear_pending_sgi() to enhance
code readability as the virtualization extensions support adds a if-else
level.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 52 ++-
1 file changed, 33 insertions(+), 19 deletions
information.
Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-zynqmp.c | 92
include/hw/arm/xlnx-zynqmp.h | 4 +-
2 files changed, 86 insertions(+), 10 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index
Implement the read and write functions for the virtual interface of the
virtualization extensions in the GICv2.
One mirror region per CPU is also created, which maps to that specific
CPU id. This is required by the GIC architecture specification.
Signed-off-by: Luc Michel
Reviewed-by: Peter
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 20 +++-
1
Add support for GICv2 virtualization extensions by mapping the necessary
I/O regions and connecting the maintenance IRQ lines.
Declare those additions in the device tree and in the ACPI tables.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/arm/virt-acpi-build.c | 6 +++--
hw
Add the read/write functions to handle accesses to the vCPU interface.
Those accesses are forwarded to the real CPU interface, with the CPU id
being converted to the corresponding vCPU id (vCPU id = CPU id +
GIC_NCPU).
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 37
generation.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c| 31 +--
hw/intc/trace-events | 12 ++--
2 files changed, 35 insertions(+), 8 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw
effect on the distributor, even in the
vCPU case, when the correponding LR has the HW field set.
Use those functions in the CPU interface code path to prepare for the
vCPU interface implementation.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 32
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off-by: Luc Michel
implement
the virtualization extensions, we report an error if the corresponding
property is set to true.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c| 2 +-
hw/intc/arm_gic_common.c | 148 ++-
hw/intc/arm
On 06/25/2018 04:23 PM, Peter Maydell wrote:
> On 19 June 2018 at 10:31, wrote:
>> From: Luc MICHEL
>>
>> This commit adds the actual implementation of the GICv2 virtualization
>> extensions logic.
>>
>> For the vCPU interfaces, most of the existing CP
On 06/25/2018 01:12 PM, Peter Maydell wrote:
> On 25 June 2018 at 05:55, Jan Kiszka wrote:
>> On 2018-06-19 11:31, luc.mic...@greensocs.com wrote:
>>> From: Luc MICHEL
>>>
>>> This patch series add support for the virtualization extensions in the
>>>
On 06/25/2018 06:55 AM, Jan Kiszka wrote:
> On 2018-06-19 11:31, luc.mic...@greensocs.com wrote:
>> From: Luc MICHEL
>>
>> This patch series add support for the virtualization extensions in the
>> ARM GICv2 interrupt controller.
>>
>> The first two commits
Implement virtualization extensions in the gic_complete_irq() function.
When a guest tries to end an IRQ that does not exist in the LRs, the
EOICount field of the virtual interface HCR register is incremented by
one, and the request is ignored.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c
Implement the maintenance interrupt generation that is part of the GICv2
virtualization extensions.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 89 +++
1 file changed, 89 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index
Implement write access to GICD_ISACTIVERn and GICD_ICACTIVERn registers
in the GICv2. Those registers allow to set or clear the active state of
an IRQ in the distributor.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 41 +++--
1 file changed, 39
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 20 +++-
1 file changed, 15 insertions
fetches the current vCPU id using the current_cpu global variable, and
one mirror region per vCPU which maps to that specific vCPU id. This is
required by the GIC architecture specification.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 71 ++-
1
a given (vCPU, irq)
pair. gic_get_lr_entry_nofail() is meant to be used in contexts where we
know for sure that the entry exists, so we can avoid the NULL check on
the returned pointer.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 5
hw/intc/gic_internal.h | 65
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