On 07/12/2018 05:41 PM, Peter Maydell wrote: > The GICD_ITARGETSR implementation still has some 11MPCore behaviour > that we were incorrectly using in our GICv1 and GICv2 implementations > for the case where the interrupt number is less than GIC_INTERNAL. > The desired behaviour here is: > * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the > CPU doing the read for irqs 29..31 > * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a > number matching the CPU doing the read for all irqs < 32 > > Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this > is an 11MPCore GIC. > > Reported-by: Jan Kiszka <jan.kis...@web.de> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > hw/intc/arm_gic.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Luc Michel <luc.mic...@greensocs.com> -- Luc
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