Implement virtualization extensions in the gic_cpu_read() and gic_cpu_write() functions. Those are the last bits missing to fully support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel <luc.mic...@greensocs.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> --- hw/intc/arm_gic.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 3cddf65826..0e1b23047e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1399,13 +1399,16 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, } break; case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno = (offset - 0xd0) / 4; + int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; - if (regno >= GIC_NR_APRS || s->revision != 2) { + if (regno >= nr_aprs || s->revision != 2) { *data = 0; + } else if (gic_is_vcpu(cpu)) { + *data = s->h_apr[gic_get_vcpu_real_id(cpu)]; } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ *data = gic_apr_ns_view(s, regno, cpu); } else { *data = s->apr[regno][cpu]; @@ -1415,11 +1418,11 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, case 0xe0: case 0xe4: case 0xe8: case 0xec: { int regno = (offset - 0xe0) / 4; if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || - gic_cpu_ns_access(s, cpu, attrs)) { + gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { *data = 0; } else { *data = s->nsapr[regno][cpu]; } break; @@ -1450,11 +1453,12 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, return MEMTX_OK; } else { s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); } } else { - s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); + int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; + s->bpr[cpu] = MAX(value & 0x7, min_bpr); } break; case 0x10: /* End Of Interrupt */ gic_complete_irq(s, cpu, value & 0x3ff, attrs); return MEMTX_OK; @@ -1467,15 +1471,18 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, } break; case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno = (offset - 0xd0) / 4; + int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; - if (regno >= GIC_NR_APRS || s->revision != 2) { + if (regno >= nr_aprs || s->revision != 2) { return MEMTX_OK; } - if (gic_cpu_ns_access(s, cpu, attrs)) { + if (gic_is_vcpu(cpu)) { + s->h_apr[gic_get_vcpu_real_id(cpu)] = value; + } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ gic_apr_write_ns_view(s, regno, cpu, value); } else { s->apr[regno][cpu] = value; } @@ -1486,10 +1493,13 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, int regno = (offset - 0xe0) / 4; if (regno >= GIC_NR_APRS || s->revision != 2) { return MEMTX_OK; } + if (gic_is_vcpu(cpu)) { + return MEMTX_OK; + } if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { return MEMTX_OK; } s->nsapr[regno][cpu] = value; break; -- 2.18.0